Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

Abstract: According to one embodiment of the present disclosure, there is provided a DC-DC converter including a slope compensation circuit configured to generate a sawtooth-shaped compensation ramp wave to output a slope voltage, a current sensing circuit configured to receive and convert a sensing current to output the converted current, and an adder configured to receive the slope voltage and the sensing current, wherein the adder includes a sensing resistor and a sensing switch, one end of the sensing resistor is connected to the current sensing circuit and the other end of the sensing resistor is connected to the sensing switch and the slope compensation circuit, and one end of the sensing switch is connected to the sensing resistor and the slope compensation circuit and the other end of the sensing switch is connected to the ground.

Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

Abstract: The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.

Abstract: A level shifter may include: a phase controller configured to determine the number of phases of a gate pulse, using an on input signal and an off input signal, and generate a control signal according to the determined number; a switching controller configured to generate one or more switching signals in response to the control signal; and an output buffer configured to generate the level-shifted gate pulse in response to the one or more switching signals.

Abstract: A power switching circuit and a method for controlling the same are disclosed herein. The power switching circuit includes a frequency control circuit, a pulse modulation circuit, and a switching convertor. The frequency control circuit receives a first reference signal driving a load, from a timing controller, and generates a second reference signal based on the first reference signal. The pulse modulation circuit generates a pulse control signal by performing pulse width modulation (PWM) or pulse frequency modulation (PFM) on the second reference signal. The switching convertor generates the voltage of output power by switching a switching element connected to the output power, in response to the pulse control signal. The pulse control signal is synchronized with the first reference signal driving the load.

Abstract: A power switching circuit and a method for controlling the same are disclosed herein. The power switching circuit includes a frequency control circuit, a pulse modulation circuit, and a switching convertor. The frequency control circuit receives a first reference signal driving a load, from a timing controller, and generates a second reference signal based on the first reference signal. The pulse modulation circuit generates a pulse control signal by performing pulse width modulation (PWM) or pulse frequency modulation (PFM) on the second reference signal. The switching convertor generates the voltage of output power by switching a switching element connected to the output power, in response to the pulse control signal. The pulse control signal is synchronized with the first reference signal driving the load.

Abstract: A level shifter may include: a phase controller configured to determine the number of phases of a gate pulse, using an on input signal and an off input signal, and generate a control signal according to the determined number; a switching controller configured to generate one or more switching signals in response to the control signal; and an output buffer configured to generate the level-shifted gate pulse in response to the one or more switching signals.

Abstract: Disclosed are a pre-driver having a modified circuit for gate pulse modulation and a power circuit including the same. The pre-driver includes a level shifter that outputs pulses having a phase difference and a gate pulse modulator that performs gate pulse modulation. The gate pulse modulator outputs a modulated gate pulse obtained by modulating a pulse by a reference voltage, and has a structure in which the number of switches provided therein is reduced.

Abstract: Disclosed are a pre-driver having a modified circuit for gate pulse modulation and a power circuit including the same. The pre-driver includes a level shifter that outputs pulses having a phase difference and a gate pulse modulator that performs gate pulse modulation. The gate pulse modulator outputs a modulated gate pulse obtained by modulating a pulse by a reference voltage, and has a structure in which the number of switches provided therein is reduced.