Abstract: A capacitor is disposed on a semiconductor substrate and includes an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate in predetermined regions, respectively. A sidewall and a bottom of the first opening are covered with a first lower electrode, and a sidewall and a bottom of the second opening is covered with a second lower electrode. Inner walls of the first and second lower electrodes are covered with an upper dielectric layer. The upper dielectric layer is covered with first and second upper electrodes at the first and second openings, respectively. A lower dielectric layer pattern intervenes between the second lower electrode and the upper dielectric layer. The method includes forming and patterning an interlayer dielectric layer on a semiconductor substrate, thereby forming an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate, respectively.

Abstract: A capacitor is disposed on a semiconductor substrate and includes an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate in predetermined regions, respectively. A sidewall and a bottom of the first opening are covered with a first lower electrode, and a sidewall and a bottom of the second opening is covered with a second lower electrode. Inner walls of the first and second lower electrodes are covered with an upper dielectric layer. The upper dielectric layer is covered with first and second upper electrodes at the first and second openings, respectively. A lower dielectric layer pattern intervenes between the second lower electrode and the upper dielectric layer. The method includes forming and patterning an interlayer dielectric layer on a semiconductor substrate, thereby forming an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate, respectively.