Patents by Inventor Yoon-sung Kim
Yoon-sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145772Abstract: An embodiment composition for solid electrolyte membranes of all-solid-state batteries includes a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities. An embodiment method of manufacturing a solid electrolyte membrane for an all-solid-state battery includes forming a composition including a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities and cross-linking the composition.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Inventors: So Yeon Kim, Yun Sung Kim, Ga Hyeon Im, Yoon Kwang Lee, Hong Seok Min, Kyu Joon Lee, Dong Won Kim, Young Jun Lee, Hui Tae Sim, Seung Bo Hong
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Publication number: 20240136499Abstract: An anodeless all-solid-state battery includes an anode current collector, a composite structure layer positioned on the anode current collector, a solid electrolyte positioned on the composite structure layer, and a cathode positioned on the solid electrolyte, in which the composite structure layer includes a carbon layer including a carbon material, and a metal deposition layer positioned on the carbon layer and including lithiophilic metal particles.Type: ApplicationFiled: August 1, 2023Publication date: April 25, 2024Inventors: GA HYEON IM, Yun Sung Kim, So Yeon Kim, Kyu Joon Lee, Hong Seok Min, Yoon Kwang Lee
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Patent number: 11967529Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.Type: GrantFiled: November 10, 2020Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
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Patent number: 11962001Abstract: Disclosed is a positive electrode material for a lithium secondary battery. The positive electrode material includes a positive electrode active material formed of Li—[Mn—Ti]-M-O-based material including a transition metal (M) to enable reversible intercalation and deintercalation of lithium and molybdenum oxide. The positive electrode active material is coated with the molybdenum oxide to form a coating layer on a surface thereof.Type: GrantFiled: October 6, 2021Date of Patent: April 16, 2024Assignees: Hyundai Motor Company, Kia Corporation, Industry Academy Cooperation Foundation of Sejong UniversityInventors: Seung Min Oh, Jun Ki Rhee, Yoon Sung Lee, Ji Eun Lee, Sung Ho Ban, Ko Eun Kim, Woo Young Jin, Sang Mok Park, Sang Hun Lee, Seung Taek Myung, Hee Jae Kim, Min Young Shin
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Patent number: 11955625Abstract: Provided are a negative electrode active material including a three-dimensional composite. The three-dimensional composite includes secondary particles containing a silicon carbide-based (SiCx, 0<x?1) nanosheet having a bent portion and amorphous carbon. Also provided are a method of producing the same, and a negative electrode and a lithium secondary battery including the negative electrode active material.Type: GrantFiled: August 20, 2021Date of Patent: April 9, 2024Assignees: SK On Co., Ltd., UNIST (Ulsan National Institute of Science and Technology)Inventors: Eunjun Park, Joon-Sup Kim, Jaekyung Sung, Yoon Kwang Lee, Tae Yong Lee, Jae Phil Cho
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Patent number: 11937476Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.Type: GrantFiled: May 4, 2023Date of Patent: March 19, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jin Sung An, Sung Ho Kim, Yong Jae Kim, Yun Hwan Park, Yoon Jee Shin, Sug Woo Jung, Hyun Wook Choi
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Patent number: 11710706Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.Type: GrantFiled: August 9, 2021Date of Patent: July 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
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Publication number: 20230118831Abstract: A map merging method for an electronic apparatus which includes: obtaining information about a first local map of a first apparatus, a pose of the first apparatus in the first local map, a second local map of a second apparatus, a pose of the second apparatus in the second local map, and an image of the second apparatus obtained by the first apparatus; identifying a relative pose of the second apparatus relative to the first apparatus from the image using a first trained artificial neural network; transforming the second local map to correspond to the first local map based on the relative pose, the pose of the first apparatus, and the pose of the second apparatus; and merging the first local map and a transformed second local map transformed in the transforming the second local map to output a merged map is provided.Type: ApplicationFiled: October 5, 2022Publication date: April 20, 2023Inventors: Byoung Tak ZHANG, Dong Sig HAN, Hyun Do LEE, Jae In KIM, Gang Hun LEE, Yoon Sung KIM
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Patent number: 11319619Abstract: A non-oriented electrical steel sheet according to an embodiment of the present invention comprises Si: 2.0 to 3.5%, Al: 0.3 to 3.5%, Mn: 0.2 to 4.5%, Zn: 0.0005 to 0.02% in wt % and Fe and inevitable impurities as a balance amount.Type: GrantFiled: December 19, 2017Date of Patent: May 3, 2022Assignee: POSCOInventors: Jae-Hoon Kim, Jong Uk Ryu, Hun Ju Lee, Yoon Sung Kim
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Patent number: 11244911Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.Type: GrantFiled: April 19, 2019Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
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Publication number: 20210366837Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
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Patent number: 11145601Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.Type: GrantFiled: June 4, 2019Date of Patent: October 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
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Patent number: 11107773Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.Type: GrantFiled: June 13, 2019Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
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Publication number: 20210057278Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
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Patent number: 10886234Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate which includes a semiconductor chip region and a scribe line region surrounding the semiconductor chip region; an insulating film arranged over the semiconductor chip region and the scribe line region on the substrate, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening portion formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate, wherein the opening portion is formed in the scribe line region, and the first surface of the insulating film and the third surface of the insulating film do not include an opening portion which expose the substrate.Type: GrantFiled: August 7, 2019Date of Patent: January 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Ho Yoon, Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jung Ho Choi
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Patent number: 10854517Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.Type: GrantFiled: March 20, 2019Date of Patent: December 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
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Publication number: 20200168556Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.Type: ApplicationFiled: June 13, 2019Publication date: May 28, 2020Inventors: HYUN-SU SIM, YOON-SUNG KIM, YUN-HEE KIM, BYUNG-MOON BAE, JUN-HO YOON
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Patent number: 10651105Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.Type: GrantFiled: January 21, 2019Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim
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Publication number: 20200126927Abstract: A semiconductor chip including an alignment patter is provided. The semiconductor ship includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.Type: ApplicationFiled: June 4, 2019Publication date: April 23, 2020Inventors: YOON SUNG KIM, YUN HEE KIM, BYUNG MOON BAE, HYUN SU SIM, JUN HO YOON, JUNG HO CHOI
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Publication number: 20200126932Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.Type: ApplicationFiled: April 19, 2019Publication date: April 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Yoon Sung KIM, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi