Abstract: Disclosed is a memory device including a plurality of memory banks, each of which performs an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data and a processing in-memory interface unit (PIM IU) that delivers signals for an operation request to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array configured to store one of the pieces of first unit data and a PIM engine that reads the one of the pieces of first unit data from the memory cell array, reads the pieces of second unit data broadcast to the plurality of memory banks, and generates an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data.

Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.

Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.

Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.

Abstract: A memory controller uses a history of the rows accessed by commands from a command queue in a command queue circuit to predict whether a second access performed immediately after the command queue becomes empty will be to a same row as a first access performed immediately before the command queue became empty. When the second access is predicted to be to a different row, the row corresponding to the first access is closed in response to the command queue becoming empty. When the second access is predicted to be to the same row, the row corresponding to the first access is not closed in response to the command queue becoming empty.

Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.

Abstract: Disclosed are a virtual memory management apparatus for avoiding error cells in a main memory and a method thereof. That is, according to the present invention, it is possible to prevent a data loss or malfunction from occurring by allocating and releasing a stack frame in a way a block including the error cells to be located between the stack frames in case of a stack region, processing the block including the error cells to be in an allocated state in a heap region memory management data structure in case of a heap region, allocating the pages including error cells to programs not used frequently via profile in case of code memory, and allocating physical memory page including the error cells to unused space of last page in case of file-mapped memory.