Patents by Inventor Yoonjee Nam

Yoonjee Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interface circuits configured to interface with multi-rank memory
    Patent number: 10073619
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
  • INTERFACE CIRCUITS CONFIGURED TO INTERFACE WITH MULTI-RANK MEMORY
    Publication number: 20180107387
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 19, 2018
    Inventors: Kwanyeob Chae, Yoonjee NAM, Ji Hun OH, Shinyoung YI, Jong-Ryun CHOI
  • Interface Circuits Configured to Interface with Multi-Rank Memory
    Publication number: 20180018092
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Application
    Filed: May 2, 2017
    Publication date: January 18, 2018
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
  • Interface circuits configured to interface with multi-rank memory
    Patent number: 9857973
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi