Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

Abstract: A semiconductor device may include a plurality of first channel structures on a substrate, a plurality of second channel structures on the substrate, a first impurity region structure between the first channel structures, a second impurity region structure between second channel structures, a third impurity region structure between the first and second channel structures, and a plurality of gate structures disposed between the first to third impurity region structures, respectively. Each of the first channel structure may have a first width, and each of the second channel structure may have a second width less than the first width. The first impurity region structure may have a first volume, and the second impurity region structure may have a second volume smaller than the first volume. The third impurity region structure may have a third volume smaller than the first volume and greater than the second volume.

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

Abstract: A semiconductor device includes a substrate including a main chip region and a scribe lane region, wherein first trenches are formed in the scribe lane region. A well region doped with impurities is provided on an upper part of the main chip region of the substrate. Align key patterns formed on surfaces of the first trenches and on surfaces of the substrate adjacent to the first trenches in the scribe lane region and having an alternately and repeatedly stacked structure of a silicon germanium pattern and a silicon pattern, are provided. A multi-bridge channel transistor is formed on the main chip region of the substrate.

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

Abstract: A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.

Abstract: A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.

Abstract: A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.

Abstract: A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.

Abstract: A semiconductor device comprising: an insulation substrate; an intrinsic semiconductor nanowire formed on the insulation substrate and having both ends doped in a p-type and an n-type, respectively and a region, which is not doped, between the doped region; doped region electrodes formed on each of the p-type doped region and the n-type doped region of the semiconductor nanowire; a lower insulation layer formed on an intrinsic region of the semiconductor nanowire; an intrinsic region electrode formed on a part of the lower insulation layer; and a metal or semiconductor nanoparticle region formed on the lower insulation layer and between the intrinsic region electrode and the doped region electrode and spaced apart from the electrodes.