Abstract: A computing system includes a host processor configured to process operations and a memory configured to include an internal processor and store host instructions to be processed by the host processor. The host processor offloads processing of a predetermined operation to the internal processor. The internal processor possibly provides specialized hardware designed to process the operation efficiently, improving the efficiency and performance of the computing system.

Abstract: Multiple-thread processing apparatuses and methods are provided. The multiple-thread processing method may include searching for loops in a plurality of threads, calculating a number of repetitions of each of found loops in respective threads among the plurality of threads, determining one or more threads based on the calculated number of repetitions of each of the found loops, dividing at least one of the one or more determined threads into child threads, and processing the child threads separately from one another in the plurality of threads.

Abstract: A power consumption control apparatus includes a resource selecting unit configured to select resources, whose power consumption levels are to be determined, from among resources of a graphic processing unit (GPU), a resource use information acquiring unit configured to determine whether the selected resources are used from a code block which is all or part of a program executed using the GPU, and a power consumption controlling unit configured to determine a power consumption level of the selected resource based on a determination result of the resource information acquiring unit and to control the power consumption level of the selected resources based on a determined power consumption level of the selected resources.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A rendering method, an apparatus for rendering an image and a rendering device are provided. The rendering method involves obtaining information about a sightline of a user, determining rendering quality based on the obtained information, and rendering a graphic image according to the determined rendering quality.

Abstract: A curve rendering method includes calculating a step size based on a length of a straight line connecting a start point and an end point among control points of a curve to be rendered, and calculating initial values of a forward differencing algorithm (FDA) based on the calculated step size and coefficient values of an equation of the curve that is determined based on the control points. The method further includes generating an FDA table based on the initial values, and calculating a coordinate value of a pixel based on the FDA table.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A computing system includes a host processor configured to process operations and a memory configured to include an internal processor and store host instructions to be processed by the host processor. The host processor offloads processing of a predetermined operation to the internal processor. The internal processor possibly provides specialized hardware designed to process the operation efficiently, improving the efficiency and performance of the computing system.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: Multiple-thread processing apparatuses and methods are provided. The multiple-thread processing method may include searching for loops in a plurality of threads, calculating a number of repetitions of each of found loops in respective threads among the plurality of threads, determining one or more threads based on the calculated number of repetitions of each of the found loops, dividing at least one of the one or more determined threads into child threads, and processing the child threads separately from one another in the plurality of threads.

Abstract: A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.

Abstract: A rendering method, an apparatus for rendering an image and a rendering device are provided. The rendering method involves obtaining information about a sightline of a user, determining rendering quality based on the obtained information, and rendering a graphic image according to the determined rendering quality.

Abstract: A power consumption control apparatus includes a resource selecting unit configured to select resources, whose power consumption levels are to be determined, from among resources of a graphic processing unit (GPU), a resource use information acquiring unit configured to determine whether the selected resources are used from a code block which is all or part of a program executed using the GPU, and a power consumption controlling unit configured to determine a power consumption level of the selected resource based on a determination result of the resource information acquiring unit and to control the power consumption level of the selected resources based on a determined power consumption level of the selected resources.

Abstract: A curve rendering method includes calculating a step size based on a length of a straight line connecting a start point and an end point among control points of a curve to be rendered, and calculating initial values of a forward differencing algorithm (FDA) based on the calculated step size and coefficient values of an equation of the curve that is determined based on the control points. The method further includes generating an FDA table based on the initial values, and calculating a coordinate value of a pixel based on the FDA table.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method of detecting a bottleneck in a data flow program includes executing the data flow program, wherein the data flow program comprises a kernel, determining a percentage of time the kernel spends on a computation, and determining the kernel to be a bottleneck upon comparing the percentage of time the kernel spends on the computation to a condition.