Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: A semiconductor device is provided including a substrate including a trench. A first conductive pattern is disposed within the trench. The first conductive pattern has a width smaller than a width of the trench. A first spacer extends along at least a portion of a side surface of the first conductive pattern and the trench. A second spacer at least partially fills the trench adjacent to the first spacer. An air spacer is provided including a first portion between the first spacer and the second spacer, and a second portion disposed on the second spacer and the first portion. A width of the second portion of the air spacer is greater than a width of the first portion of the air spacer.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.