Patents by Inventor Yoram Betser
Yoram Betser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150340098Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Spansion LLCInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 8995201Abstract: Disclose is a non-volatile memory (NVM) cell sensing circuit. The sensing circuit may include a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell. Conditioning may include adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase. The conditioning circuit segment may also be adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase. Adjusting a charge density within the NVM cell sense-side-line may include inducing current in the sense-side-line in a direction opposite to the sensing current.Type: GrantFiled: November 7, 2013Date of Patent: March 31, 2015Assignee: Spansion LLCInventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 8760930Abstract: A source-sensing configuration for non-volatile memory devices to simultaneously read 2 bits in two different memory cells sharing a same word line is disclosed. In a first cell arrangement, a drain of a first read cell is biased and its source and that of two adjacent cells in a direction towards the second read cell are connected through source bit lines to a source sense amplifier. In a second cell arrangement, the drain of the second read cell is biased and its source and that of its two adjacent cells in a direction towards the first read cell are connected through source bit lines to a source sense amplifier. A memory cell acts as a cell pipe and joins together the first and second cell arrangements. Driving all six source bit lines simultaneously allows the 2 bits to be simultaneously read while maintaining currents due to pipe effect substantially minimized.Type: GrantFiled: February 18, 2013Date of Patent: June 24, 2014Assignee: Spansion LLC.Inventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 8593881Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: GrantFiled: November 22, 2011Date of Patent: November 26, 2013Assignee: Spansion Israel LtdInventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Publication number: 20120063238Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: ApplicationFiled: November 22, 2011Publication date: March 15, 2012Inventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Patent number: 8098525Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: GrantFiled: September 17, 2008Date of Patent: January 17, 2012Assignee: Spansion Israel LtdInventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Patent number: 7864588Abstract: A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.Type: GrantFiled: September 17, 2008Date of Patent: January 4, 2011Assignee: Spansion Israel Ltd.Inventors: Yoram Betser, Yair Sofer, Oren Shlomo, Avri Harush
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Patent number: 7605579Abstract: The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.Type: GrantFiled: November 21, 2006Date of Patent: October 20, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Yoram Betser, Alexander Kushnarenko, Oleg Dadashev
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Patent number: 7532529Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: GrantFiled: August 14, 2006Date of Patent: May 12, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Oleg Dadashev, Yoram Betser, Eduardo Maayan
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Publication number: 20090073774Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: ApplicationFiled: September 17, 2008Publication date: March 19, 2009Inventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Publication number: 20090073760Abstract: A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.Type: ApplicationFiled: September 17, 2008Publication date: March 19, 2009Inventors: Yoram Betser, Yair Sofer, Oren Shlomo, Avri Harush
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Patent number: 7466594Abstract: A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifierType: GrantFiled: July 19, 2006Date of Patent: December 16, 2008Assignee: Saifun Semiconductors Ltd.Inventors: Yair Sofer, Eduardo Maayan, Yoram Betser
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Publication number: 20080239599Abstract: A clamping scheme using dual sensing detection, which can sense and differentiate (in the extreme) between a high voltage level and fast (enough) slope (indicative of ESD), and low voltage level and slow slope (indicative of normal operation) and/or low voltage level and fast slope (indicative of hot insertion). It can also generate a locking scheme to ensure proper discharging only if the level is above high level and fast slope. It can also operate the clamping for a short time only if the level is below the high level but above the low level, and of sufficient slope.Type: ApplicationFiled: April 1, 2007Publication date: October 2, 2008Inventors: Yehuda Yizraeli, Yoram Betser, Ilan Bloom
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Publication number: 20080094127Abstract: Measuring and controlling current consumption and output current of a charge pump by measuring a first current coming into the charge pump; and measuring a second current coming into a driver for at least one of the one or more stages of the charge pump. A control loop may one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages, or by decreasing the current consumption by adjusting a load connected to the output of the charge pump pipe. The first and second currents may be compared with first and second reference currents. A load connected to the charge pump may comprise non-volatile memory cells, and the charge pump may be implemented on a same integrated circuit chip as the memory cells.Type: ApplicationFiled: November 21, 2006Publication date: April 24, 2008Inventors: Yoram Betser, Alexander Kushnarenko, Oleg Dadashev
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Patent number: 7256438Abstract: A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.Type: GrantFiled: June 8, 2004Date of Patent: August 14, 2007Assignee: Saifun Semiconductors LtdInventors: Joseph S. Shor, Eduardo Maayan, Yoram Betser
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Publication number: 20070171717Abstract: A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifierType: ApplicationFiled: July 19, 2006Publication date: July 26, 2007Applicant: Saifun Semiconductors Ltd.Inventors: Yair Sofer, Eduardo Maayan, Yoram Betser
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Patent number: 7190212Abstract: Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.Type: GrantFiled: June 8, 2004Date of Patent: March 13, 2007Assignee: Saifun Semiconductors LtdInventors: Joseph S. Shor, Yoram Betser, Yair Sofer
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Patent number: 7187595Abstract: A replenish circuit for a semiconductor memory device, including a bias current generating unit adapted to generate a bias current, a frequency controllable oscillator adapted to receive the bias current and to provide an oscillating output, and a pulse generator adapted to receive the oscillating output and to generate first and second pulses as a function of the oscillating output, the second pulse being embedded in the first pulse, the first pulse causing the bias current generating unit to be connected to a power supply, and the second pulse being fed to sample-and-hold circuitry adapted to sample the bias current and hold the value thereof during the first pulse.Type: GrantFiled: June 8, 2004Date of Patent: March 6, 2007Assignee: Saifun Semiconductors Ltd.Inventors: Yair Sofer, Ori Elyada, Yoram Betser
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Patent number: 7184313Abstract: The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading.Type: GrantFiled: June 17, 2005Date of Patent: February 27, 2007Assignee: Saifun Semiconductors Ltd.Inventors: Yoram Betser, Yair Sofer, Eduardo Maayan
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Publication number: 20060285402Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: ApplicationFiled: August 14, 2006Publication date: December 21, 2006Applicant: SAIFUN SEMICONDUCTORS LTD.Inventors: Oleg Dadashev, Yoram Betser, Eduardo Maayan