Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.

Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection.

Abstract: A radio (10) with a burst event execution and time synchronization apparatus (16) executes instructions during and after performing time synchronization between a mobile unit and a base station. Both base station (12) and mobile radio (10) have internal timer units (26, 16). Mobile radio (10) timing unit (16) is reset during synchronization between the mobile radio (10) and the base station (12). The control unit (18) writes instructions I(i) including their execution times T(i) to a memory bank (42) within the mobile radio (10). Execution logic (32) within mobile radio (10) executes instruction operands O(i) when execution time T(i) is equal or smaller then a timing count signal received from the timer unit (16). When a time synchronization reset causes the radio (10) time count to jump past queued instructions they can be executed immediately in a burst or delayed until the next communication frame.

Abstract: A method and a device for performing stack operations within a processing system. A first and second stack pointers point to a top of a stack and to a memory location following the top of the stack. A first stack pointer is used during pop operations and a second stack pointer is used during push operations. When a stack pointer is selected, it replaces the other stack pointer. The selected memory pointer is provided to a memory module in which a stack is implemented, and is also updated. When a pop operation is executed the updated stack pointer points to a memory location preceding a memory location pointed by the selected stack pointer and when a push operation is executed the updated stack pointer points to a memory address following that address.

Abstract: A power saving device and method for either adding or subtracting a constant from an operand, by checking a logic value of a portion of the operand and deciding whether to activate a multi-bit adder or to perform the subtraction or addition by inverting a portion of the operand. The power saving device and method is especially efficient when the constant K equals 2n. Then, the n'th bit of the operand is checked and if the addition or subtraction operation can be performed by inverting the n'th bit of the operand, a result is generated by that inversion, while a multi-bit adder is disabled.

Abstract: A mobile radio (10) with a synchronization apparatus (14) executes a method (60) for time synchronizing the radio (10) and a base station (12). Base station (12) and radio (10) have internal timers (26, 16). A control unit (18) in the radio (10) receives a signal (29) from the base station (12) and determines the difference F between timers (26, 16, 30) in the base (12) and mobile (10). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the radio (10). One of these instructions I(N) reloads the radio timing counter (30) with a corrected value C=f(F,B) at a predetermined time T(N)=B which avoids conflicts with other operations of the radio (10).

Abstract: Embodiments of the present invention relate generally to digital signal processing. One embodiment contemplates a method for performing a digital signal processing operation having a first data word located at a misaligned starting address within a first memory. The method includes outputting the first data word to a register file during a first internal. During a second interval, the method further includes reading a second data word and a third data word from the first memory where the second data word is output to the register file and the third data word is output to the first buffer. Embodiments also contemplate a digital signal processor having a register filed capable of receiving one data word from a memory and one data word from a buffer during each of a series of processing intervals for performing a digital signal operation.

Abstract: The Viterbi algorithm (20) is performed with a reduced number of calculations when the comparing step (C, 80, 50) is anticipated before the selecting (S, 62, 64, 66, 68) and adding steps (A, 74, 76). During comparing (C), selection decisions (e.g., D (i)) are obtained by analyzing pairs of old path metrics (e.g., P (2i, j−1) at 91, P (2i+1, j−1) at 92) by subtracting and multiplying the path metrics with branch metrics (e.g., B (i, j) at 95) and combining intermediate sign (e.g., SP, SB, S&Dgr;) by e.g., and-logic (50). Selecting decisions (e.g., D (i/2, j+1), D (i/2+N/2, j+1) and new path metrics (e.g., P (i, j), P (i+12, j) are continuously stored and updated.

Abstract: A radio (10) executes a method (100) for entering and exiting a halt status. Radio (10) has a control unit (18) and an internal timing unit (16). The timing unit (16) has execution logic (32), a status register (46) a counter (30) and a clock source (37). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the execution logic (32). One of these instructions is a ‘SWITCH CLOCK’ instruction causing the timing unit (16) to switch between clock signals. One of the instructions is ‘HALT COUNTER’ causing the radio (10) to enter a halt state. The radio (10) can be synchronized to the end of a first communication frame received by it after exiting a halt state.

Abstract: The invention relates to a digital signal processor in which two multiply accumulate operations are carried out in one machine cycle. Only one address generation unit is required for addressing two data words of both the X and Y memories, since in the main processing loop the least significant address bit is considered as "Don't care", so that an access operation to the memory results in two output data words at a time.

Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.

Abstract: A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.

Abstract: In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82).