Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: A system for combining power includes a plurality of branches and a secondary winding. The plurality of branches are configured to provide branch power. Each of the branches contribute to the branch power at non-peak power. The secondary winding is configured to combine the branch power from the plurality of branches into an output power.

Abstract: A system for combining power includes a plurality of branches and a secondary winding. The plurality of branches are configured to provide branch power. Each of the branches contribute to the branch power at non-peak power. The secondary winding is configured to combine the branch power from the plurality of branches into an output power.

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Abstract: Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.

Abstract: A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.

Abstract: Architectures including digital outphasing transmitters. Digital signal generation circuitry generates at least two base-band sinusoid signals. Bandpass modulation circuitry is coupled to receive the base-band sinusoid signals and generates at least two modulated digital signals. Power amplifiers are coupled to receive the modulated digital signals to amplify the modulated digital signals. The amplified modulated signals are combined and transmitted.

Abstract: A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.

Abstract: Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.

Abstract: A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.

Abstract: Architectures including digital outphasing transmitters.

Abstract: A radio frequency identification (RFID) system may use passive RFID tags that harvest electrical energy from a received signal and store that harvested electrical energy in a capacitor. The stored electrical energy may then be used to transmit from the RFID tag after the received signal has stopped. To decrease the size of the capacitor that is needed, the RFID tag may transmit only briefly, and then use a subsequent received signal to charge up the capacitor for another brief transmission. In some embodiments, each transmission only represents a single binary bit, but a series of such transmissions may be used to transmit multiple bits. Some embodiments may use a radio frequency of 10's of gigahertz.