Abstract: The level shift device of the present invention comprises: a level shift circuit which converts a voltage level of a single input signal; and a duty correcting circuit which offsets a difference in the duty of an output signal of the level shift circuit with respect to the duty of the input signal.

Abstract: The level shift device of the present invention comprises: a level shift circuit which converts a voltage level of a single input signal; and a duty correcting circuit which offsets a difference in the duty of an output signal of the level shift circuit with respect to the duty of the input signal.

Abstract: A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where a match line is activated and a consistency cancel circuit for forcibly making the match line inactive when a word line and a write instruction signal are both activated. When a write operation and a retrieve operation are simultaneously instructed, a result of the retrieval is forcibly judged to be inconsistent at a write address, thereby it is unnecessary to prohibit the simultaneous execution of the write operation and the retrieve operation.

Abstract: A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where a match line is activated and a consistency cancel circuit for forcibly making the match line inactive when a word line and a write instruction signal are both activated. When a write operation and a retrieve operation are simultaneously instructed, a result of the retrieval is forcibly judged to be inconsistent at a write address, thereby it is unnecessary to prohibit the simultaneous execution of the write operation and the retrieve operation.

Abstract: In a priority circuit, priority processing is rapidly performed without lowering the voltage level of a signal propagated through serially connected transistors. When the priority circuit is placed in a non-operational state by turning off an NMOS transistor in accordance with a precharge enable signal, potentials on propagating signal nodes and a HIT output terminal are precharged to H potential by PMOS transistors used for precharging. Therefore, when the NMOS transistor is turned on and the priority circuit enters an operational state, if input signals include a H-level signal, the lowering of the voltage level of a propagated signal is suppressed in increasing the potentials on the propagating signal nodes and the HIT output terminal to the H potential by PMOS transistors used for detecting a HIT signal. Thus, malfunction derived from noise can be prevented.

Abstract: In a priority circuit, priority processing is rapidly performed without lowering the voltage level of a signal propagated through serially connected transistors. When the priority circuit is placed in a non-operational state by turning off an NMOS transistor in accordance with a precharge enable signal, potentials on propagating signal nodes and a HIT output terminal are precharged to H potential by PMOS transistors used for precharging. Therefore, when the NMOS transistor is turned on and the priority circuit enters an operational state, if input signals include a H-level signal, the lowering of the voltage level of a propagated signal is suppressed in increasing the potentials on the propagating signal nodes and the HIT output terminal to the H potential by PMOS transistors used for detecting a HIT signal. Thus, malfunction derived from noise can be prevented.