Abstract: A clock provider system (100) receives an input clock X1 and, shifted by 90.degree., an input clock X2 and provides output clock Y as a free selectable logical function Y=f(X1, X2). A signal provider (103) comprises non-inverting delay units (150) and inverting delay units (160) each forwarding the input clocks X1 and X2 with a substantially equal delay. According to the required logical function, a distributor unit (170) sends the delayed signals to control inputs of a switch matrix (100) for providing intermediate signal Z. At the output, an inverter (102) inverts Z and provides Y. In the switch matrix (100), transistor chains (115, 116, 125, 126) alternatively pull an intermediate node (130, signal Z) either to a first (191) or to a second (192) reference potential. Thereby, near reference transistors (111, 114, 121, 124) are made conductive prior to near node transistors (112, 113, 122, 123).