Abstract: A mechanism for evaluating a floating-point accuracy of a vehicle driving compatible compiler includes testing code compiled by a vehicle driving compatible compiler with code compiled by a testing environment compatible compiler, executing the vehicle driving compatible compiled code involves executing addition type floating points operations to provide a first floating point result, executing the testing environment compatible compiled code to perform addition type floating points operations to provide a second floating point result that corresponds to the first floating point result, comparing the first floating point result to the second floating point results to provide a comparison result, and determining the floating-point accuracy of vehicle driving compatible compiler based on the comparison result.

Abstract: Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.

Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.

Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

Abstract: Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.

Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.

Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.

Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per lane, wherein J? is less than N multiplied by K?.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.

Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.

Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.

Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.