Abstract: A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Abstract: An advanced encryption standard (AES) engine with real time S-box generation includes a Galois field multiplier system in a first mode responsive to a first data block for generating an AES selection (S-box) function by executing the multiplicative increase in GF1(2m) and applying an affine over GF(2) transformation to obtain a subbyte transformation; and a shift register system for transforming the subbyte transformation to obtain a shift row transformation; the Galois field multiplier system is responsive in a second mode to the shift row transformation to obtain a mix column transformation and add a round key for generating in real time an advanced encryption standard cipher function of the first data block.

Abstract: A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an identification number for uniquely identifying each cell and its dedicated line and a communication port including at least one parallel to serial transmitter circuit in each cell for broadcasting its cell's output data over its dedicated line; at least one serial to parallel receiver circuit in each cell; each cell responsive to the identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell and a configuration register associated with each receiver circuit and responsive to the local configuration command to condition its receiver's circuit to receive serial input data broadcast from the pre-selected cell's dedicated line.

Abstract: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Abstract: A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m−2 times where m is the degree of the Galois field to obtain the reciprocal of the first Galois field element, and multiplying in the Galois field reciprocal engine the reciprocal of the first Galois field element by a second Galois field element for predicting the modulo remainder of the polynomial product for an irreducible polynomial to obtain the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input ex

Abstract: A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.

Abstract: A Galois field multiplier system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; and a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficients for predicting the modulo remainder for predetermined irreducible polynomial.

Abstract: A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normalization scale factor to obtain the maximum butterfly output without overflow from this stage; determines from the butterfly outputs of this stage the minimum normalizing exponent for the butterfly outputs of this stage and predicts a normalization scale factor of the next stage from the minimum normalizing exponent of this stage and a stage guard scale value to obtain the maximum butterfly output without overflow from that next stage.

Abstract: A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits including identifying successive sets of m bits in a stream of data bits and simultaneously comparing each of the sets of m bits to the predetermined bit pattern for detecting the presence of the predetermined bit pattern in the stream of data.

Abstract: A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

Abstract: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an identification number for uniquely identifying each cell and its dedicated line and a communication port including at least one parallel to serial transmitter circuit in each cell for broadcasting its cell's output data over its dedicated line; at least one serial to parallel receiver circuit in each cell; each cell responsive to the identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell and a configuration register associated with each receiver circuit and responsive to the local configuration command to condition its receiver's circuit to receive serial input data broadcast from the pre-selected cell's dedicated line.

Abstract: A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Abstract: A programmable data encryption engine for performing the cipher function of an advanced encryption standard (AES) algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF−1(28) and applying an affine over GF(2) transformation to obtain a subbyte transformation and in a second mode to the subbyte transformation to transform the subbyte transformation to obtain a shift row transformation, and a Galois field multiplier for transforming the shift row transformation to obtain a mix column transformation and add a round key resulting in an advanced encryption standard cipher function of the first data block.

Abstract: A Galois field linear transformer includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includes a plurality of cells, each cell including an exclusive OR logic circuit and AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transformation of the inputs in a single cycle.

Abstract: A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a storage plane representing a function for enabling the cells of the matrix which defines that function; and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data.

Abstract: A Galois field multiply/multiply-add/multiply-accumulate system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficient for predicting the modulo remainder for a predetermined irreducible polynomial; and a Galois field adder circuit for adding the product of the multiplier circuit with a third polynomial with coefficients over a Galois field for performing the multiplication and add operations in a single cycle.