Abstract: Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.

Abstract: Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to measure a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Procedures are also provided for assessing the accuracy of the power-per-processing event values and for controlling further operations based on the assessment.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, continuous data-transfer to and from a memory device of the data storage device. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to indirectly delay the transfer without stopping toggling the DQS signals. The toggle mode (TM) speed is dynamically modified slowly during the transfer while considering the current level of the internal write buffer just before writing to the memory device. The transfer can now be accelerated or deaccelerated dynamically during the data transfer. The changes are done slowly so signal integrity issues are avoided.

Abstract: Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Abstract: A device, for example a memory system, is disclosed wherein two or more operational modes may be set. The clock toggle rate and ODT resistors are dynamically controlled based on one or more of a desired margin of signal integrity, performance, cooling rate, and power consumption.

Abstract: A device, for example a memory system, is disclosed wherein two or more operational modes may be set. The clock toggle rate and ODT resistors are dynamically controlled based on one or more of a desired margin of signal integrity, performance, cooling rate, and power consumption.

Abstract: A method includes receiving, at an error correction coding (ECC) controller, information indicating one or more data chunks to be decoded, populating a schedule according to an order of decoding of the data chunks, and initiating decode of the data chunks according to the schedule.

Abstract: A method includes receiving, at an error correction coding (ECC) controller, information indicating one or more data chunks to be decoded, populating a schedule according to an order of decoding of the data chunks, and initiating decode of the data chunks according to the schedule.