Abstract: An up-drain type MOSFET device is formed in a limited n+ diffusion region used for an up-drain structure with the reduction of increase in a chip area which would otherwise be required for such device. Trench 112 is made separately from device regions provided in n?-type exitaxial layer 101. Trench 112 reaches to n+ implanted layer 111 while deeply diffused n+ region 110 is formed along a sidewall of trench 112 by applying slant implantation thereby to form an up-drain structure.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer. 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: An optical semiconductor relay comprises a light emitting element converting an electrical signal into an optical signal, a first photodiode array receiving the optical signal from the light emitting element. The first photodiode array converts the optical signal into an electrical signal. The relay is further provided with a first diode having one electrode connected to one end of the first photodiode array and a MOSFET. The MOSFET has a gate terminal connected to other electrode of the first diode, and a source terminal connected to other end of the first photodiode array. A second photodiode array is arranged to receive the optical signal from the light emitting element. The second photodiode array converts the optical signal into an electrical signal and has both ends connected to the respective electrodes of the first diode. A control circuit connected between the gate and source terminals of the MOSFET.

Abstract: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.

Abstract: The MOSFET according to the embodiment of the present invention has an n− type layer 3 formed on the support substrate 1 via a first insulating layer 2. In the active layer 3, an n+ type drain layer 7 and a p type base layer 5 are formed at portions away from each other. An n+ type source layer 6 is formed in a surface region of the base layer 5. A trench gate is formed across the source layer 6, the base layer 5 and the active layer 3. A part of the side wall of the trench gate 10 is in contact with the base layer 5 and the source layer 6 via a second insulating layer 8.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: In a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.

Abstract: A bidirectional semiconductor switch employs two insulated gate semiconductor devices such as insulated gate bipolar transistors (IGBTs) that are connected oppositely in parallel, with the collector of one of the IGBTs being connected to the emitter of the other. The gates of the IGBTs are biased by gate controllers that are potentially independent of each other. The semiconductor switch is capable of controlling a direct current as well as an alternating current at a low ON-state voltage, reducing a conduction loss, and improving efficiency.

Abstract: A semiconductor relay has two output MOSFET pairs, each of which is series-connected with the other. Each MOSFET pair is comprised of two MOSFETs series-connected oppositely to each other, and these MOSFETs are controlled to turn on or off simultaneously. The semiconductor relay further includes a switch, which is inserted between the ground and the junction of the two MOSFET pairs. When these MOSFETs are in an off condition, said switch is closed in order to release electric charges accumulated on said MOSFETs and to increase the off-resistance of this semiconductor relay. On the other hand, when the MOSFETs are in an on condition, said switch is opened so as to connect both MOSFET pairs in series. As a result, a semiconductor relay having a high off-resistance can be obtained without increasing the on-resistance.

Abstract: A photo-coupler apparatus has a light emitting element in the primary side. The secondary side of this apparatus is comprised of a photoelectromotive diode array, a light sensitive impedance element series-connected to said array, a drive transistor, and at least one output MOSFET connected to the output terminals of this apparatus. The light sensitive impedance element comes into a large impedance state when an optical signal from the light emitting element is weak. In this case, the light sensitive impedance element generates a sufficient voltage to activate the drive transistor, in spite of the photocurrent being small. This results in an improvement of the dynamic sensitivity of this apparatus. When said optical signal is strong, the impedance element comes into a small impedance state, thus providing the MOSFET with a sufficient photo-current. This results in the shortening of switching times of the output MOSFET.

Abstract: A photocoupler apparatus includes a light emitting diode, a first photodiode array which generates a first electromotive force by being activated with a light signal from the light emitting element, and an output MOSFET which is driven by the first electromotive force. This apparatus further includes a current limiting circuit and a second photodiode array which generates a second electromotive force by being activated with the light signal from the light emitting diode. The current limiting circuit controls the behavior of the MOSFET so as to limit an output current below a predetermined value. In addition, this circuit is driven by the second electromotive force generated by the second photodiode array. So, the whole resistance of this apparatus as a product can be greatly reduced and a photocoupler apparatus having a high current capacity can easily be obtained in this invention.

Abstract: A semiconductor device includes a plurality of lead frames on which at least one semiconductor pellet is formed, a dummy pellet on at least one of the plurality of lead frames, wires for connecting electrodes of the semiconductor pellets with electrodes of the dummy pellet.

Abstract: A photocoupler apparatus comprises an output MOSFET, a series circuit of a first photoelectromotive force diode array and a diode and connected to the gate and substrate of the MOSFET, a series circuit of a second photoelectromotive force diode array and a resistor and connected between both ends of the diode, and a normally-ON drive transistor. The diode is connected in a forward bias direction to the direction of a light current generated by the first diode array. When a charge current to be supplied to the MOSFET is large, most of the light current flows through the forward-biased diode to the output MOSFET and is not influenced by the current limitation by the resistor. When the charge current decreases, the diode is reverse-biased and the gate-substrate voltage of the MOSFET is higher than a voltage generated across the first diode array.