Abstract: A DPD (1) includes: a polynomial structure including a pseudo-interpolation/sub-sample-shift processing unit (101) configured to operate at a sampling rate for sampling an input signal not upsampled in a previous stage of the DPD (1), pseudo-interpolate a sample point between sample points of the input signal, and shift the pseudo-interpolated sample point by a sub-sample and a multiplexer (109) configured to select a combination of a sub-sample shift amount; and an FIR filter (107) configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample. The DPD (1) compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the DPD (1), by using the polynomial structure and the FIR filter (107).

Abstract: A DPD (1) includes: a polynomial structure including a pseudo-interpolation/sub-sample-shift processing unit (101) configured to operate at a sampling rate for sampling an input signal not upsampled in a previous stage of the DPD (1), pseudo-interpolate a sample point between sample points of the input signal, and shift the pseudo-interpolated sample point by a sub-sample and a multiplexer (109) configured to select a combination of a sub-sample shift amount; and an FIR filter (107) configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample. The DPD (1) compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the DPD (1), by using the polynomial structure and the FIR filter (107).

Abstract: In an amplification apparatus according to the present disclosure, a combining unit combines an output signal of a first amplifier provided at a first branch with an output signal of a second amplifier provided at a second branch and outputs the combined signal. A non-linearity compensation unit multiplies an input baseband signal by a non-linearity compensation coefficient for compensating non-linearity of the entire apparatus, a first deviation compensation unit multiplies a first branch signal by a first deviation compensation coefficient for compensating an inter-branch deviation, and a second deviation compensation unit multiplies a second branch signal by a second deviation compensation coefficient for compensating the inter-branch deviation.

Abstract: A DPD operates at a sampling rate at which the input signal not up sampled at an upstream of the DPD is sampled. The DPD includes a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample, and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample. The DPD uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Abstract: In an amplification apparatus according to the present disclosure, a combining unit combines an output signal of a first amplifier provided at a first branch with an output signal of a second amplifier provided at a second branch and outputs the combined signal. A non-linearity compensation unit multiplies an input baseband signal by a non-linearity compensation coefficient for compensating non-linearity of the entire apparatus, a first deviation compensation unit multiplies a first branch signal by a first deviation compensation coefficient for compensating an inter-branch deviation, and a second deviation compensation unit multiplies a second branch signal by a second deviation compensation coefficient for compensating the inter-branch deviation.

Abstract: A DPD operates at a sampling rate at which the input signal not up sampled at an upstream of the DPD is sampled. The DPD includes a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample, and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample. The DPD uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Abstract: A peak suppressing device (10) includes: a subtracting unit (11) that subtracts a predetermined threshold from an amplitude value of an input signal and generates a first peak signal; a multiplying unit (12) that multiplies the first peak signal by a weight coefficient and generates a second peak signal; a band limiting filter (13) that limits a band of the second peak signal, and generates a third peak signal; a subtracting unit (14) that subtracts the third peak signal from the input signal; and a weight coefficient generating unit (15) that generates the weight coefficient based on a value, the value being an amplitude value of the first peak signal divided by an amplitude value of a fourth peak signal generated when a convolution arithmetic operation is performed on by using at least a tap coefficient used in a center tap of the band limiting filter (13).

Abstract: The transmission circuit includes a comparator that converts a phase-modulated signal from an orthogonal modulator into a pulse signal so as to use the pulse signal as the sampling clock of the a delta-sigma modulator, and an asynchronous clock transfer unit and an interpolating circuit, disposed between a circuit operating based on the baseband clock and the delta-sigma modulator. The asynchronous clock transfer unit converts the amplitude component signal synchronized with the baseband clock, into an amplitude component signal synchronized with an N-frequency divided clock obtained by dividing the frequency of the sampling clock by N. The interpolating circuit interpolates the output signal from the asynchronous clock transfer unit so that the amount of change of one sample in the N-frequency divided clock becomes equal to the amount of change of one sample in the sampling clock.

Abstract: The transmission circuit includes a comparator that converts a phase-modulated signal from an orthogonal modulator into a pulse signal so as to use the pulse signal as the sampling clock of the a delta-sigma modulator, and an asynchronous clock transfer unit and an interpolating circuit, disposed between a circuit operating based on the baseband clock and the delta-sigma modulator. The asynchronous clock transfer unit converts the amplitude component signal synchronized with the baseband clock, into an amplitude component signal synchronized with an N-frequency divided clock obtained by dividing the frequency of the sampling clock by N. The interpolating circuit interpolates the output signal from the asynchronous clock transfer unit so that the amount of change of one sample in the N-frequency divided clock becomes equal to the amount of change of one sample in the sampling clock.

Abstract: A peak suppressing device (10) includes: a subtracting unit (11) that subtracts a predetermined threshold from an amplitude value of an input signal and generates a first peak signal; a multiplying unit (12) that multiplies the first peak signal by a weight coefficient and generates a second peak signal; a band limiting filter (13) that limits a band of the second peak signal, and generates a third peak signal; a subtracting unit (14) that subtracts the third peak signal from the input signal; and a weight coefficient generating unit (15) that generates the weight coefficient based on a value, the value being an amplitude value of the first peak signal divided by an amplitude value of a fourth peak signal generated when a convolution arithmetic operation is performed on by using at least a tap coefficient used in a center tap of the band limiting filter (13).

Abstract: Provided is a power consumption control circuit, an amplifier circuit and a power consumption control method which control the power consumption associated with an amplification action in real time. A power consumption control circuit of the present invention comprises: a detection means which detects the presence or absence of an input of a digital input signal, spending a first period of time; a signal delay means which delays the digital input signal by a second period of time equivalent to the first period of time, and outputs the delayed signal; a digital-to-analog conversion means which converts the delayed signal into an analog signal, and outputs the analog signal; an amplification means which generates an amplification action when a bias is applied to it; and a bias control means which applies a bias to an amplification device, on the basis of a detection result obtained by the detection means.

Abstract: A distortion compensation amplifier that performs distortion compensation with a pre-distortion scheme. The distortion compensation amplifier includes a power detection unit (1), a distortion compensation aspect storing unit (3), a distortion providing unit (4) for performing distortion compensation, and an amplifier for amplifying a signal. Feedback signal taking section (9, 11 to 16) for taking a feedback signal, and a distortion level detecting section (9, 11, 12, 17, and 18) for detecting the level of distortion contained in the feedback signal. A controller (19) updates the storage content of the distortion compensation aspect storing unit so as to reduce the error component between the signal to be amplified and the feedback signal at the time of start of distortion compensation processing, and updates the content of the distortion compensation aspect storing unit so as to reduce the detected level of distortion when the error component is reduced.

Abstract: A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the peak signal according to time detection position; a complex filter section limiting the weighted peak signal within a band of the input signal; a filter coefficient calculation section calculating filter coefficients of the complex filter section; a delay adjustment section delaying another of the branched input signals by a time period required for calculating the band-limited peak signal; and a subtraction section subtracting the band-limited peak signal from the other of the branched input signals subjected to delay.

Abstract: Provided is a power consumption control circuit, an amplifier circuit and a power consumption control method which control the power consumption associated with an amplification action in real time. A power consumption control circuit of the present invention comprises: a detection means which detects the presence or absence of an input of a digital input signal, spending a first period of time; a signal delay means which delays the digital input signal by a second period of time equivalent to the first period of time, and outputs the delayed signal; a digital-to-analog conversion means which converts the delayed signal into an analog signal, and outputs the analog signal; an amplification means which generates an amplification action when a bias is applied to it; and a bias control means which applies a bias to an amplification device, on the basis of a detection result obtained by the detection means.

Abstract: To accelerate the convergence of distortion compensation and improve the performance of distortion compensation in a distortion compensation amplifier which performs distortion compensation with a pre-distortion scheme. Level detecting means 1, distortion compensation aspect storing means 3, distortion providing means 4 perform distortion compensation, and amplifying means 8 amplifies a signal. Feedback signal taking means 9, 11 to 16 take a feedback signal, and distortion level detecting means 9, 11, 12, 17, and 18 detect the level of distortion contained in the feedback signal. Control means 19 updates the storage content of the distortion compensation aspect storing means so as to reduce the error component between the signal to be amplified and the feedback signal at the time of start of distortion compensation processing, and updates the content of the distortion compensation aspect storing means so as to reduce the detected level of distortion when the error component is reduced.

Abstract: A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the peak signal according to time detection position; a complex filter section limiting the weighted peak signal within a band of the input signal; a filter coefficient calculation section calculating filter coefficients of the complex filter section; a delay adjustment section delaying another of the branched input signals by a time period required for calculating the band-limited peak signal; and a subtraction section subtracting the band-limited peak signal from the other of the branched input signals subjected to delay.

Abstract: Disclosed is a distortion compensation circuit that reduces the time for convergence of distortion compensation data, without impairing any stability of distortion compensation. The circuit includes an error computation and compensation data updating section that repeats a computation in which errors between an input orthogonal baseband transmission signal and a feedback signal obtained by demodulating part of the output from a power amplifier are computed to obtain error data and values obtained by multiplying this error data by step coefficients are added to distortion compensation data before updating, thereby computing distortion compensation data after updating. Distortion compensation data for compensation of nonlinear distortion is thus updated. Step coefficients are stored in a step coefficient data memory with respect to each of different input signal amplitude values.

Abstract: A power calculating and amplitude limitation judging portion 13 calculates the power value x of the digital quadrature baseband signal I, Q from a transmission data generator 1, and compares the power value x with a power threshold value y set by a threshold value setting portion 14 to judge whether amplitude limitation is needed or not. An amplitude maximum limiting portion 12 subjects the quadrature baseband signal from the transmission data generator 1 to the amplitude maximum value limitation based on the judgment result in the power calculating and amplitude limitation judging portion 13. Thereafter, the digital quadrature baseband signal which has been subjected to the amplitude maximum value limitation by the amplitude maximum value limiting portion 12 is subjected to the distortion compensation using complex multiplication based on the distortion compensation data by a non-linear distortion compensation calculator 2.

Abstract: An apparatus includes an amplitude converter, receiving a complex baseband signal to output an amplitude thereof, a memory, receiving an amplitude from the amplitude converter as an address to output an inverse gain associated with the amplitude, a reciprocal converter receiving an output of the memory as input and outputting a reciprocal of the memory output, a FIR filter for filtering an output signal of the reciprocal converter, a reciprocal converter receiving an output of the FIR filter as input to output a reciprocal of the output of the FIR filter, and a complex multiplier for executing complex multiplication of the complex baseband signal and an output of the reciprocal converter.

Abstract: A multiport amplifying apparatus according to the present invention implements each of individual hybrids, which make up an input hybrid network, with a digital quadrature baseband 90-degree hybrid circuit, and can therefore eliminate a gain deviation and phase deviation among lines in the input hybrid network. Consequently, gain deviation and phase deviation values among the lines, required to the overall apparatus, can be distributed only to amplifiers and an output RF-band hybrid network, thus facilitating optimal designing. Further, the input hybrid network can be largely reduced in size and cost because it processes signals in a digital quadrature baseband signal domain.