Patents by Inventor Yoshiaki Emoto
Yoshiaki Emoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6717250Abstract: A plurality of semiconductor chips electrically connected to wires formed on a carrier tape are aligned in order to provide a small semiconductor apparatus with good heat radiation. An electronic device using this semiconductor apparatus as the carrier tape is folded inward and wound in a spiral shape, and layers are laminated so that fabrication can be good. After this carrier tape is folded inward, sequentially wound in a spiral shape, and layers of the semiconductor chips are laminated, they are covered by a molding resin.Type: GrantFiled: October 17, 2000Date of Patent: April 6, 2004Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Publication number: 20040063247Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.Type: ApplicationFiled: September 18, 2003Publication date: April 1, 2004Inventor: Yoshiaki Emoto
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Patent number: 6664643Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.Type: GrantFiled: May 10, 2001Date of Patent: December 16, 2003Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Patent number: 6646335Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.Type: GrantFiled: July 19, 2002Date of Patent: November 11, 2003Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Patent number: 6593648Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.Type: GrantFiled: August 30, 2001Date of Patent: July 15, 2003Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Publication number: 20030045029Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.Type: ApplicationFiled: May 10, 2001Publication date: March 6, 2003Inventor: Yoshiaki Emoto
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Publication number: 20020180022Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.Type: ApplicationFiled: July 19, 2002Publication date: December 5, 2002Applicant: SEIKO EPSON CORPORATIONInventor: Yoshiaki Emoto
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Patent number: 6441476Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.Type: GrantFiled: October 18, 2000Date of Patent: August 27, 2002Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Publication number: 20020030252Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.Type: ApplicationFiled: August 30, 2001Publication date: March 14, 2002Applicant: SEIKO EPSON CORPORATIONInventor: Yoshiaki Emoto
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Patent number: 6118173Abstract: A semiconductor device of this invention includes a semiconductor chip on which a device is formed, inner leads reaching the periphery of the semiconductor chip, and bonding wires for electrically connecting the semiconductor chip and the inner leads. The semiconductor chip is fixed on a die pad portion, and a chip fixing inner lead is integrated with the die pad portion. To simplify the bonding wire connection process and improve the reliability, the chip fixing inner lead has a step portion so that the die pad portion is formed at a lower position than the inner leads. The step portion is formed so as to be offset from a line of the end portions of the inner leads in the opposite direction of the semiconductor chip, so an arbitrary bonding wire can be kept apart from the step portion.Type: GrantFiled: November 13, 1997Date of Patent: September 12, 2000Assignee: Nippon Steel Semiconductor CorporationInventor: Yoshiaki Emoto
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Patent number: 5422163Abstract: A flexible substrate to be used for assemblage of a semiconductor chip having connecting points to be electrically connected to an external side, comprises a base film unit made of a flexible synthetic resin and including a mounting portion for mounting thereon a semiconductor chip, groups of conductive leads formed on a surface of the base film unit, each lead group including a plurality of the leads formed so as to extend from respective positions in the mounting portion corresponding to the connecting points of the semiconductor chip as mounted in the mounting portion to selected positions on the base film unit, and a plurality of projections each formed at an area between adjacent two of the lead groups on the surface of the base film unit and having a height substantially equal to the height of the leads of the lead group.Type: GrantFiled: December 10, 1993Date of Patent: June 6, 1995Assignee: Nippon Steel CorporationInventors: Tadashi Kamiyama, Yoshiaki Emoto
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Patent number: 5362984Abstract: A semiconductor device is disclosed in which connection between electrodes of a semiconductor element and/or between a plurality of semiconductor elements can be made in one package to the utmost. More particularly, electrodes of two IC chips 12a and 12b are bonded to leader leads 16a and interconnection leads 16b.sub.5 patterned on a film. Connections of the interconnection leads 16b.sub.1 and 16b.sub.2 to 16b.sub.4 and 16b.sub.3 which are impossible by the leads, are made in such a manner that pads 24b.sub.1, 24b.sub.4 and 24b.sub.2, 24b.sub.3 formed on the interconnection leads are connected correspondingly by using bonding wires as jumping wires. After the connection, the IC chips, the leads and the bonding wires are resin-sealed over an overall region encompassed by a region 27.Type: GrantFiled: February 24, 1992Date of Patent: November 8, 1994Assignee: Nippon Steel CorporationInventors: Masashi Konda, Toshio Yamamoto, Yoshiaki Emoto
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Patent number: 5223454Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the firstType: GrantFiled: September 17, 1991Date of Patent: June 29, 1993Assignee: Hitachi, Ltd.Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
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Patent number: 5188280Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.Type: GrantFiled: December 23, 1991Date of Patent: February 23, 1993Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
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Patent number: 5090609Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.Type: GrantFiled: April 26, 1990Date of Patent: February 25, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
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Patent number: 5049972Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the firstType: GrantFiled: June 26, 1990Date of Patent: September 17, 1991Assignee: Hitachi, Ltd.Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda