Patents by Inventor Yoshiaki Emoto

Yoshiaki Emoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6717250
    Abstract: A plurality of semiconductor chips electrically connected to wires formed on a carrier tape are aligned in order to provide a small semiconductor apparatus with good heat radiation. An electronic device using this semiconductor apparatus as the carrier tape is folded inward and wound in a spiral shape, and layers are laminated so that fabrication can be good. After this carrier tape is folded inward, sequentially wound in a spiral shape, and layers of the semiconductor chips are laminated, they are covered by a molding resin.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: April 6, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiaki Emoto
  • Publication number: 20040063247
    Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.
    Type: Application
    Filed: September 18, 2003
    Publication date: April 1, 2004
    Inventor: Yoshiaki Emoto
  • Patent number: 6664643
    Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: December 16, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiaki Emoto
  • Patent number: 6646335
    Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: November 11, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiaki Emoto
  • Patent number: 6593648
    Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 15, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiaki Emoto
  • Publication number: 20030045029
    Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.
    Type: Application
    Filed: May 10, 2001
    Publication date: March 6, 2003
    Inventor: Yoshiaki Emoto
  • Publication number: 20020180022
    Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.
    Type: Application
    Filed: July 19, 2002
    Publication date: December 5, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiaki Emoto
  • Patent number: 6441476
    Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: August 27, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiaki Emoto
  • Publication number: 20020030252
    Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 14, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiaki Emoto
  • Patent number: 6118173
    Abstract: A semiconductor device of this invention includes a semiconductor chip on which a device is formed, inner leads reaching the periphery of the semiconductor chip, and bonding wires for electrically connecting the semiconductor chip and the inner leads. The semiconductor chip is fixed on a die pad portion, and a chip fixing inner lead is integrated with the die pad portion. To simplify the bonding wire connection process and improve the reliability, the chip fixing inner lead has a step portion so that the die pad portion is formed at a lower position than the inner leads. The step portion is formed so as to be offset from a line of the end portions of the inner leads in the opposite direction of the semiconductor chip, so an arbitrary bonding wire can be kept apart from the step portion.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: September 12, 2000
    Assignee: Nippon Steel Semiconductor Corporation
    Inventor: Yoshiaki Emoto
  • Patent number: 5422163
    Abstract: A flexible substrate to be used for assemblage of a semiconductor chip having connecting points to be electrically connected to an external side, comprises a base film unit made of a flexible synthetic resin and including a mounting portion for mounting thereon a semiconductor chip, groups of conductive leads formed on a surface of the base film unit, each lead group including a plurality of the leads formed so as to extend from respective positions in the mounting portion corresponding to the connecting points of the semiconductor chip as mounted in the mounting portion to selected positions on the base film unit, and a plurality of projections each formed at an area between adjacent two of the lead groups on the surface of the base film unit and having a height substantially equal to the height of the leads of the lead group.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: June 6, 1995
    Assignee: Nippon Steel Corporation
    Inventors: Tadashi Kamiyama, Yoshiaki Emoto
  • Patent number: 5362984
    Abstract: A semiconductor device is disclosed in which connection between electrodes of a semiconductor element and/or between a plurality of semiconductor elements can be made in one package to the utmost. More particularly, electrodes of two IC chips 12a and 12b are bonded to leader leads 16a and interconnection leads 16b.sub.5 patterned on a film. Connections of the interconnection leads 16b.sub.1 and 16b.sub.2 to 16b.sub.4 and 16b.sub.3 which are impossible by the leads, are made in such a manner that pads 24b.sub.1, 24b.sub.4 and 24b.sub.2, 24b.sub.3 formed on the interconnection leads are connected correspondingly by using bonding wires as jumping wires. After the connection, the IC chips, the leads and the bonding wires are resin-sealed over an overall region encompassed by a region 27.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: November 8, 1994
    Assignee: Nippon Steel Corporation
    Inventors: Masashi Konda, Toshio Yamamoto, Yoshiaki Emoto
  • Patent number: 5223454
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 29, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
  • Patent number: 5188280
    Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: February 23, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5090609
    Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: February 25, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5049972
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 17, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda