Patents by Inventor Yoshiaki Hagi
Yoshiaki Hagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456363Abstract: An indium phosphide crystal substrate has a diameter of 100-205 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of sulfur is from 2.0×1018 to 8.0×1018 cm?3, the indium phosphide crystal substrate has an average dislocation density of 10-500 cm?2, and when am atomic concentration of tin is from 1.0×1018 to 4.0×1018 cm?3 or an atomic concentration of iron is from 5.0×1015 to 1.0×1017 cm?3, the indium phosphide crystal substrate has an average dislocation density of 500-5000 cm?2.Type: GrantFiled: February 23, 2018Date of Patent: September 27, 2022Assignee: Sumitomo Electric Industries, Ltd.Inventors: Muneyuki Nishioka, Kazuaki Konoike, Takuya Yanagisawa, Yasuaki Higuchi, Yoshiaki Hagi
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Patent number: 11421344Abstract: A gallium nitride crystal substrate has a diameter of 50-155 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion in a part of an outer edge. The gallium nitride crystal substrate contains any of oxygen atoms, silicon atoms, and carriers at a concentration of 2×1017 to 4×1018 cm?3, and has an average dislocation density of 1000 to 5×107 cm?2 in any of a first flat region extending over a width from the flat portion to a position at a distance of 2 mm in a direction perpendicular to a straight line indicating the flat portion in a main surface and a first notch region extending over a width from the notch portion to a position at a distance of 2 mm in a direction perpendicular to a curve indicating the notch portion in the main surface.Type: GrantFiled: February 23, 2018Date of Patent: August 23, 2022Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yusuke Yoshizumi, Hideki Osada, Shugo Minobe, Yoshiaki Hagi
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Patent number: 11408091Abstract: A gallium arsenide crystal substrate has a diameter not smaller than 150 mm and not greater than 205 mm and a thickness not smaller than 300 ?m and not greater than 800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of silicon is not lower than 3.0×1016 cm?3 and not higher than 3.0×1019 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 0 cm?2 and not higher than 15000 cm?2, and when an atomic concentration of carbon is not lower than 1.0×1015 cm?3 and not higher than 5.0×1017 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 3000 cm?2 and not higher than 20000 cm?2.Type: GrantFiled: February 23, 2018Date of Patent: August 9, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masanori Morishita, Hidetoshi Takayama, Yasuaki Higuchi, Yoshiaki Hagi
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Publication number: 20200255979Abstract: A gallium nitride crystal substrate has a diameter of 50-155 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion in a part of an outer edge. The gallium nitride crystal substrate contains any of oxygen atoms, silicon atoms, and carriers at a concentration of 2×1017 to 4×1018 cm?3, and has an average dislocation density of 1000 to 5×107 cm?2 in any of a first flat region extending over a width from the flat portion to a position at a distance of 2 mm in a direction perpendicular to a straight line indicating the flat portion in a main surface and a first notch region extending over a width from the notch portion to a position at a distance of 2 mm in a direction perpendicular to a curve indicating the notch portion in the main surface.Type: ApplicationFiled: February 23, 2018Publication date: August 13, 2020Applicant: Sumitomo Electric Industries, Ltd.Inventors: Yusuke YOSHIZUMI, Hideki OSADA, Shugo MINOBE, Yoshiaki HAGI
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Publication number: 20200131668Abstract: A gallium arsenide crystal substrate has a diameter not smaller than 150 mm and not greater than 205 mm and a thickness not smaller than 300 ?m and not greater than 800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of silicon is not lower than 3.0×1016 cm?3 and not higher than 3.0×1019 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 0 cm?2 and not higher than 15000 cm?2, and when an atomic concentration of carbon is not lower than 1.0×1015 cm?3 and not higher than 5.0×1017 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 3000 cm?2 and not higher than 20000 cm?2.Type: ApplicationFiled: February 23, 2018Publication date: April 30, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masanori MORISHITA, Hidetoshi TAKAYAMA, Yasuaki HIGUCHI, Yoshiaki HAGI
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Publication number: 20200066850Abstract: An indium phosphide crystal substrate has a diameter of 100-205 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of sulfur is from 2.0×1018 to 8.0×1018 cm?3, the indium phosphide crystal substrate has an average dislocation density of 10-500 cm?2, and when an atomic concentration of tin is from 1.0×1015 to 4.0×1018 cm?3 or an atomic concentration of iron is from 5.0×1015 to 1.0×1017 cm?3, the indium phosphide crystal substrate has an average dislocation density of 500-5000 cm?2.Type: ApplicationFiled: February 23, 2018Publication date: February 27, 2020Applicant: Sumitomo Electric Industries, Ltd.Inventors: Muneyuki NISHIOKA, Kazuaki KONOIKE, Takuya YANAGISAWA, Yasuaki HIGUCHI, Yoshiaki HAGI
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Patent number: 10533265Abstract: Relates to a method of producing a semiconductor crystal having generation of a defect suppressed in the semiconductor single crystal. The production method includes the steps of: forming a boron oxide film (31) on the inner wall of a growth container (10) having a bottom section and a body section continuous to the bottom section; bringing the boron oxide film (31) into contact with boron oxide melt containing silicon oxide to form a boron oxide film (32) containing silicon oxide on the inner wall of the growth container (10); forming raw material melt (34) above seed crystal (20) placed in and on the bottom section of the growth container (10); and solidifying the raw material melt (34) from the seed crystal (20) side to grow a semiconductor single crystal.Type: GrantFiled: September 13, 2017Date of Patent: January 14, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Sakurada, Tomohiro Kawase, Yoshiaki Hagi
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Publication number: 20180010262Abstract: Relates to a method of producing a semiconductor crystal having generation of a defect suppressed in the semiconductor single crystal. The production method includes the steps of: forming a boron oxide film (31) on the inner wall of a growth container (10) having a bottom section and a body section continuous to the bottom section; bringing the boron oxide film (31) into contact with boron oxide melt containing silicon oxide to form a boron oxide film (32) containing silicon oxide on the inner wall of the growth container (10); forming raw material melt (34) above seed crystal (20) placed in and on the bottom section of the growth container (10); and solidifying the raw material melt (34) from the seed crystal (20) side to grow a semiconductor single crystal.Type: ApplicationFiled: September 13, 2017Publication date: January 11, 2018Inventors: Takashi SAKURADA, Tomohiro KAWASE, Yoshiaki HAGI
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Patent number: 9797068Abstract: Relates to a method of producing a semiconductor crystal having generation of a defect suppressed in the semiconductor single crystal. The production method includes the steps of: forming a boron oxide film on the inner wall of a growth container having a bottom section and a body section continuous to the bottom section; bringing the boron oxide film into contact with boron oxide melt containing silicon oxide to form a boron oxide film containing silicon oxide on the inner wall of the growth container; forming raw material melt above seed crystal placed in and on the bottom section of the growth container; and solidifying the raw material melt from the seed crystal side to grow a semiconductor single crystal.Type: GrantFiled: March 28, 2011Date of Patent: October 24, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Sakurada, Tomohiro Kawase, Yoshiaki Hagi
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Publication number: 20130008370Abstract: Relates to a method of producing a semiconductor crystal having generation of a defect suppressed in the semiconductor single crystal. The production method includes the steps of: forming a boron oxide film on the inner wall of a growth container having a bottom section and a body section continuous to the bottom section; bringing the boron oxide film into contact with boron oxide melt containing silicon oxide to form a boron oxide film containing silicon oxide on the inner wall of the growth container; forming raw material melt above seed crystal placed in and on the bottom section of the growth container; and solidifying the raw material melt from the seed crystal side to grow a semiconductor single crystal.Type: ApplicationFiled: March 28, 2011Publication date: January 10, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takashi Sakurada, Tomohiro Kawase, Yoshiaki Hagi
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Patent number: 7473317Abstract: A crystal growth crucible made of boron nitride includes a cylindrical tip portion for accommodating a seed crystal, and a cylindrical straight-body portion for growing a crystal, which is formed above the tip portion and has a diameter larger than that of the tip portion. Thickness T1 of the tip portion and thickness T2 of the straight-body portion satisfy a condition of 0.1 mm?T2<T1?5 mm, and inside diameter D2 and length L2 of the straight-body portion satisfy conditions of 100 mm<D2 and 2<L2/D2<5.Type: GrantFiled: March 9, 2006Date of Patent: January 6, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventor: Yoshiaki Hagi
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Publication number: 20080127885Abstract: A crystal growth crucible made of boron nitride includes a cylindrical tip portion for accommodating a seed crystal, and a cylindrical straight-body portion for growing a crystal, which is formed above the tip portion and has a diameter larger than that of the tip portion. Thickness T1 of the tip portion and thickness T2 of the straight-body portion satisfy a condition of 0.1 mm?T2<T1?5 mm, and inside diameter D2 and length L2 of the straight-body portion satisfy conditions of 100 mm<D2 and 2<L2/D2 <5.Type: ApplicationFiled: March 9, 2006Publication date: June 5, 2008Inventor: Yoshiaki Hagi
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Patent number: 6758899Abstract: A crystal growth vessel for growing a crystal within a main container has a crystal growth starting portion in which the crystal starts to grow, whereas the crystal growth starting portion is formed from a material having a thermal conductivity higher than that of a material of the main container.Type: GrantFiled: April 25, 2002Date of Patent: July 6, 2004Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yoshiaki Hagi, Shigeto Kato
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Publication number: 20030066478Abstract: A crystal growth vessel for growing a crystal within a main container has a crystal growth starting portion in which the crystal starts to grow, whereas the crystal growth starting portion is formed from a material having a thermal conductivity higher than that of a material of the main container.Type: ApplicationFiled: April 25, 2002Publication date: April 10, 2003Inventors: Yoshiaki Hagi, Shigeto Kato
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Patent number: 6402838Abstract: A crystal growth vessel for growing a crystal within a main container has a crystal growth starting portion in which the crystal starts to grow, whereas the crystal growth starting portion is formed from a material having a thermal conductivity higher than that of a material of the main container.Type: GrantFiled: July 31, 2000Date of Patent: June 11, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yoshiaki Hagi, Shigeto Kato
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Patent number: 6180269Abstract: A GaAs single crystal substrate and an epitaxial wafer using the same suppress the generation of slips during growth of the epitaxial layer, and improve the breakdown withstanding characteristic of devices fabricated on such substrates. The GaAs single crystal substrate has a mean dislocation density in plane of at most 2×104 cm−2, a carbon concentration of 2.5 to 20.0×1015 cm−3, a boron concentration of 2.0 to 20.0×1016 cm−3, an impurity concentration other than carbon and boron of at most 1×1017 cm−3, an EL2 concentration of 5.0 to 10.0×1015 cm−3, resistivity of 1.0 to 5.0×108 &OHgr;·cm and a mean residual strain measured by photoelastic analysis of at most 1.0×10−5.Type: GrantFiled: June 16, 1999Date of Patent: January 30, 2001Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yoshiaki Hagi, Ryusuke Nakai
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Patent number: 5728212Abstract: A compound semiconductor crystal has a reduced dislocation density. The compound semiconductor crystal doped with an impurity satisfies the following relations, wherein c.c. represents its carrier concentration and .eta. represents its activation factor:.eta..ltoreq.c.c./(7.8.times.10.sup.15) (1).eta..ltoreq.(10/19).times.(197-2.54.times.10.sup.-17 .times.c.c.) (2).eta..gtoreq.c.c./(3.6.times.10.sup.16) (3)A method which can prepare a compound semiconductor crystal doped with an impurity and having a prescribed carrier concentration with excellent reproducibility comprises the steps of melting a raw material for the compound semiconductor crystal in a crucible, and controlledly cooling the obtained raw material melt, thereby growing a crystal. The time required for cooling the raw material melt from the melting point T of the raw material to 2/3T is so controlled as to adjust the carrier concentration to a prescribed level.Type: GrantFiled: September 19, 1996Date of Patent: March 17, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tetsuya Inoue, Yoshiaki Hagi
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Patent number: 5612014Abstract: A compound semiconductor crystal has a reduced dislocation density reduced. The compound semiconductor crystal doped with an impurity satisfies the following relations, wherein c.c. represents its carrier concentration and .eta. represents its activation factor:.eta..ltoreq.c.c./(7.8.times.10.sup.15) (1).eta..ltoreq.(10/19).times.(197-2.54.times.10.sup.-17 .times.c.c.) (2).eta..gtoreq.c.c./(3.6.times.10.sup.16) (3)A method which can prepare a compound semiconductor crystal doped with an impurity and having a prescribed carrier concentration with excellent reproducibility comprises the steps of melting a raw material for the compound semiconductor crystal in a crucible, and controllably cooling raw material melt, making thereby growing a crystal. The time required for cooling the raw material melt from the melting point T of the raw material to 2/3T is so controlled as to adjust the carrier concentration to a prescribed level.Type: GrantFiled: July 31, 1995Date of Patent: March 18, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tetsuya Inoue, Yoshiaki Hagi