Patents by Inventor Yoshiaki Harasawa
Yoshiaki Harasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10396718Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.Type: GrantFiled: January 15, 2018Date of Patent: August 27, 2019Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshiaki Harasawa, Fuminori Morisawa
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Publication number: 20180152151Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.Type: ApplicationFiled: January 15, 2018Publication date: May 31, 2018Inventors: Yoshiaki HARASAWA, Fuminori MORISAWA
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Patent number: 9912300Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.Type: GrantFiled: February 17, 2017Date of Patent: March 6, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshiaki Harasawa, Fuminori Morisawa
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Publication number: 20170179892Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.Type: ApplicationFiled: February 17, 2017Publication date: June 22, 2017Inventors: Yoshiaki HARASAWA, Fuminori MORISAWA
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Patent number: 8649741Abstract: A radio frequency module is configured to enter a power saving mode with high reliability. The radio frequency module includes, e.g., a first switch transistor for coupling a transmission node to an antenna, a second switch transistor for shunting the transmission node to a ground voltage, and a level shift circuit for performing on-off control of the first and second switch transistors by positive and negative power supply voltages.Type: GrantFiled: August 5, 2011Date of Patent: February 11, 2014Assignee: Renesas Electronics CorporationInventors: Masanori Iijima, Yoshiaki Harasawa
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Patent number: 8633618Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.Type: GrantFiled: October 15, 2012Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventors: Masanori Iijima, Yoshiaki Harasawa
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Patent number: 8546980Abstract: There is provided a radio-frequency module and a radio communication system capable of supporting multiple bands at low cost or small size. A high-frequency power amplifier device includes a power amplifier circuit unit for GSM and a control circuit outputting antenna switch control signals with a VSW1 level or a VSW2 level in response to a mode setting signal for selecting GSM or W-CDMA. The VSW2 level is generated by boosting the VSW1 level using a clock signal from an oscillation circuit. When GSM is selected by the mode setting signal, the high-frequency power amplifier device stops the oscillation circuit and outputs the antenna switch control signals of the VSW1 level to an antenna switch device. When W-CDMA is selected by the mode setting signal, the high-frequency power amplifier device outputs the antenna switch control signals of the VSW2 level to the antenna switch device, using the oscillation circuit.Type: GrantFiled: December 8, 2011Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Kenichi Shimamoto, Yoshiaki Harasawa, Tadashi Matsuoka
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Publication number: 20130038505Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.Type: ApplicationFiled: October 15, 2012Publication date: February 14, 2013Inventors: Masanori IIJIMA, Yoshiaki HARASAWA
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Patent number: 8324760Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.Type: GrantFiled: July 13, 2010Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Masanori Iijima, Yoshiaki Harasawa
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Publication number: 20120163247Abstract: There is provided a radio-frequency module and a radio communication system capable of supporting multiple bands at low cost or small size. A high-frequency power amplifier device includes a power amplifier circuit unit for GSM and a control circuit outputting antenna switch control signals with a VSW1 level or a VSW2 level in response to a mode setting signal for selecting GSM or W-CDMA. The VSW2 level is generated by boosting the VSW1 level using a clock signal from an oscillation circuit. When GSM is selected by the mode setting signal, the high-frequency power amplifier device stops the oscillation circuit and outputs the antenna switch control signals of the VSW1 level to an antenna switch device. When W-CDMA is selected by the mode setting signal, the high-frequency power amplifier device outputs the antenna switch control signals of the VSW2 level to the antenna switch device, using the oscillation circuit.Type: ApplicationFiled: December 8, 2011Publication date: June 28, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi SHIMAMOTO, Yoshiaki HARASAWA, Tadashi MATSUOKA
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Publication number: 20120064952Abstract: A radio frequency module is configured to enter a power saving mode with high reliability. The radio frequency module includes, e.g., a first switch transistor for coupling a transmission node to an antenna, a second switch transistor for shunting the transmission node to a ground voltage, and a level shift circuit for performing on-off control of the first and second switch transistors by positive and negative power supply voltages.Type: ApplicationFiled: August 5, 2011Publication date: March 15, 2012Applicant: Renesas Electronics CorporationInventors: Masanori Iijima, Yoshiaki Harasawa
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Patent number: 8095094Abstract: A communication semiconductor integrated circuit includes a phase control loop and an amplitude control loop. A gain of a variable gain amplifier when it is detected from an output of the comparator that the amplitudes of the reference signal and the feedback signal are equal to each other while a predetermined DC voltage is applied to an amplifier which amplifies an output of a transmission oscillation circuit and is controlled by the amplitude control loop to vary the gain of the variable gain amplifier on a feedback path is held in a register. Thereafter, the DC voltage is changed to another value to detect the gain of the variable gain amplifier, so that the gain of a variable gain amplifier on the forward path is decided on the basis of the detected gain and the gain held in the register.Type: GrantFiled: November 3, 2008Date of Patent: January 10, 2012Assignees: Renesas Electronics Corporation, TTPCOM LimitedInventors: Hiroaki Matsui, Taizo Yamawaki, Yoshiaki Harasawa, Steve Williams
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Publication number: 20110074220Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.Type: ApplicationFiled: July 13, 2010Publication date: March 31, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masanori IIJIMA, Yoshiaki HARASAWA
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Patent number: 7725124Abstract: An object of the present invention is to provide a transmitter-receiver RF-IC having a built-in regulator, which can reduce a minimum value of an input voltage of the regulator without increasing its area, the input voltage being supplied from a battery, the transmitter-receiver RF-IC being capable of normal operation with the input voltage, whereby the operating time of a mobile terminal can be improved as compared with the prior art. According to the present invention, in order to achieve the above object, an output end of a regulator built into a RF-IC is first led to the outside of the RF-IC. Then, the output end is led to an area in proximity to the circuit block by use of wiring on a mobile terminal substrate whose resistance is low, or by use of wiring on a module whose resistance is low, thereby shortening the wiring length inside the RF-IC.Type: GrantFiled: October 11, 2005Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Taizo Yamawaki, Yoshiaki Harasawa
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Patent number: 7519337Abstract: A transmitter employing variable gain amplifiers and operating with both constant and nonconstant envelope modulation systems is contrived to suppress variation in the transmitting power when constant envelope modulation is performed. The transmitter comprises a PM loop, an AM loop, and a variable gain amplifier which is shared by the PM loop and the AM loop and combines phase information that the PM loop outputs and envelope information that the AM loop outputs by gain control. The variable gain amplifier comprises a variable gain amplifier body having a supply voltage terminal and a bias current detection terminal for extracting a bias current corresponding to a gain, wherein the gain changes with a change in the potential of the supply voltage terminal, and a bias control block connected to the supply voltage terminal and the bias current detection terminal.Type: GrantFiled: December 16, 2005Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Masahiro Ito, Taizo Yamawaki, Yoshiaki Harasawa
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Publication number: 20090068967Abstract: A communication semiconductor integrated circuit includes a phase control loop and an amplitude control loop. A gain of a variable gain amplifier when it is detected from an output of the comparator that the amplitudes of the reference signal and the feedback signal are equal to each other while a predetermined DC voltage is applied to an amplifier which amplifies an output of a transmission oscillation circuit and is controlled by the amplitude control loop to vary the gain of the variable gain amplifier on a feedback path is held in a register. Thereafter, the DC voltage is changed to another value to detect the gain of the variable gain amplifier, so that the gain of a variable gain amplifier on the forward path is decided on the basis of the detected gain and the gain held in the register.Type: ApplicationFiled: November 3, 2008Publication date: March 12, 2009Inventors: Hiroaki Matsui, Taizo Yamawaki, Yoshiaki Harasawa, Steve Williams
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Patent number: 7486142Abstract: The present invention is directed to compensate electric properties of an RF power module depending on changes with time, temperature dependency, variations, and the like of grounded emitter current amplification factor of an HBT. A compound semiconductor integrated circuit supplies reference current of a reference HBT depending on hFE of an HBT to an input terminal of a first current mirror of a bias circuit of a silicon semiconductor integrated circuit. The base of an output HBT of the compound semiconductor integrated circuit is biased with bias current which increases in response to decrease in hFE of the HBT from an output of the first current mirror of the silicon semiconductor integrated circuit.Type: GrantFiled: December 29, 2006Date of Patent: February 3, 2009Assignee: Renesas Technology Corp.Inventors: Hirokazu Tsurumaki, Hiroyuki Nagai, Tomio Furuya, Yoshiaki Harasawa, Makoto Tabei
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Patent number: 7463876Abstract: A communication semiconductor integrated circuit includes a phase control loop and an amplitude control loop. A gain of a variable gain amplifier when it is detected from an output of the comparator that the amplitudes of the reference signal and the feedback signal are equal to each other while a predetermined DC voltage is applied to an amplifier which amplifies an output of a transmission oscillation circuit and is controlled by the amplitude control loop to vary the gain of the variable gain amplifier on a feedback path is held in a register. Thereafter, the DC voltage is changed to another value to detect the gain of the variable gain amplifier, so that the gain of a variable gain amplifier on the forward path is decided on the basis of the detected gain and the gain held in the register.Type: GrantFiled: March 9, 2006Date of Patent: December 9, 2008Assignees: Renesas Technolog Corp., TTPCOM LimitedInventors: Hiroaki Matsui, Taizo Yamawaki, Yoshiaki Harasawa, Steve Williams
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Patent number: 7444123Abstract: With a dual mode transmitter capable of handling two modulation methods for nonconstant amplitude modulation and constant amplitude modulation, respectively, speed-up of transition between modes is implemented. In a mode handling the constant amplitude modulation, first capacitors included in a low-pass filter constituting an AM loop, and a second capacitor included in an integrator are kept recharged from a first constant-voltage power supply and a second constant-voltage power supply by use of a first switch and a second switch, respectively. By doing so, a value of voltage to be recharged at the time of a mode changeover is decreased, and further, a first variable-gain amplifier starts control of a gain while avoiding a region where the output voltage of the first variable-gain amplifier has slow response against an input voltage.Type: GrantFiled: January 20, 2006Date of Patent: October 28, 2008Assignee: Renesas Technology Corp.Inventors: Taizo Yamawaki, Yoshiaki Harasawa
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Patent number: 7340232Abstract: The invention provides a receiving system and a transmitting system capable of decreasing an offset between differential signals and between quadrature signals and improving a manufacturing yield and a semiconductor integrated circuit device for processing a wireless communication signal having therein the systems. A receiving system includes: a local oscillator for generating an oscillation signal in a desired frequency; a 90-degree phase-shifting circuit for generating a signal by shifting a phase of the oscillation signal output from the local oscillator by 90 degrees; a first mixer for mixing one of differential reception signals with an output signal of the first 90-degree phase-shifting circuit and outputting frequency-converted differential signals; and a second mixer for mixing another one of the differential reception signals with an output signal of the local oscillator and outputting frequency-converted differential signals.Type: GrantFiled: May 11, 2004Date of Patent: March 4, 2008Assignee: Renesas Technology Corp.Inventors: Motoki Murakami, Yutaka Igarashi, Akio Yamamoto, Isao Ikuta, Yoshiaki Harasawa