Patents by Inventor Yoshiaki Hiratsuka

Yoshiaki Hiratsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200364393
    Abstract: A non-transitory computer-readable recording medium storing a bypass capacitor arrangement selection program for causing a computer to execute a process, the process includes: setting a first power supply pin of one or more power supply pins located closest to a first signal pin of one or more signal pins, as a power supply pin to which a capacitor for noise countermeasure is coupled, in a circuit component including the one or more signal pins and the one or more power supply pins; and displaying the first power supply pin and a first mark indicating the capacitor for the noise countermeasure in a circuit diagram including display of the circuit component.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki NAKAO, Yoshiaki Hiratsuka, Kenji NAGASE
  • Patent number: 10839588
    Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory and configured to receive a designation of a progression degree in which a circuit pattern displayed on a two-dimensional model of a printed circuit board is traced from a start point to an end point of the circuit pattern, display, on the two-dimensional model, the circuit pattern from the start point to a point corresponding to the progression degree on a three-dimensional model of the printed circuit board based on a setting of the start point and the end point of the circuit pattern, and display the circuit pattern of the two-dimensional model to distinguish a first pattern to form a part of the circuit pattern and a second pattern to form a part of the circuit pattern, the first pattern and the second pattern having portions overlapping each other.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Nagase, Yoshiaki Hiratsuka, Tomoyuki Nakao
  • Publication number: 20200293710
    Abstract: A non-transitory computer-readable storage medium for storing a program which causes a processor to perform processing for calculating a coupling route of mechanical parts, the processing includes: extracting, from CAD data, information on each of a plurality of routes through which electricity is capable of flowing from a plurality of the mechanical parts constituting a conductive structure excluding an electronic part mounted over a substrate, to the substrate; extracting each of a coupling surface and a coupling point between the mechanical parts or between the mechanical part and the electronic part; calculating each of distances between the extracted coupling points; selecting a route having a shortest distance among the plurality of routes from a specific mechanical part in the plurality of mechanical parts to the substrate; and outputting the selected shortest route.
    Type: Application
    Filed: February 5, 2020
    Publication date: September 17, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Koji DEMIZU
  • Publication number: 20200082593
    Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory and configured to receive a designation of a progression degree in which a circuit pattern displayed on a two-dimensional model of a printed circuit board is traced from a start point to an end point of the circuit pattern, display, on the two-dimensional model, the circuit pattern from the start point to a point corresponding to the progression degree on a three-dimensional model of the printed circuit board based on a setting of the start point and the end point of the circuit pattern, and display the circuit pattern of the two-dimensional model to distinguish a first pattern to form a part of the circuit pattern and a second pattern to form a part of the circuit pattern, the first pattern and the second pattern having portions overlapping each other.
    Type: Application
    Filed: August 6, 2019
    Publication date: March 12, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Kenji NAGASE, Yoshiaki Hiratsuka, Tomoyuki NAKAO
  • Publication number: 20190266304
    Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer to execute a procedure, the procedure includes generating a search range configured to include a constituent point for constituting a line which approximates a center route of a string-like component or a band-like component disposed in a device at which an influence of electromagnetic noise is verified, checking whether there is an interference between the search range and a range around a component mounted on the device, and visualizing a result of the checking.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 29, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Koji DEMIZU
  • Patent number: 10346582
    Abstract: A coupling distance y of a plurality of securing elements for coupling two members to construct a casing for accommodating a circuit board having electric components mounted thereon inside space surrounded by a conductor extracted from design data, an overlapping width x of overlap sections provided to the two members for coupling the two members with the plurality of securing elements, the overlap sections contacting to each other, and a wavelength ? of electromagnetic noises generated from the electric components, are extracted. Then, a recommended coupling distance Y for the plurality of securing elements to attenuate the electromagnetic noises by a certain attenuation amount is calculated, based on the overlapping width x and the wavelength ?, and the coupling distance y is compared with the recommended coupling distance Y. Thereby, verifications of an electromagnetic noise countermeasure can be made reliably without relying on settings by a user.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Kai Nojima, Kenji Nagase, Yoshinori Mesaki
  • Publication number: 20190114386
    Abstract: A recording medium recording a program that causes a computer to execute a process includes acquiring data including information indicating a shape and a position of a fastening member having a cylindrical fastening portion and information indicating a shape and a position of a fastened member having a hole in which an inner wall is disposed to be isolated from an outer periphery of the fastening portion, generating distance information of a distance between the outer periphery of the fastening portion and the inner wall, determining whether the fastening member and the fastened member are fitted based on the distance information, determining, when the fastening member and the fastened member are fitted, whether materials of the fastening member and the fastened member are conductive, and outputting, when the materials are conductive, continuity information indicating that the fastening member and the fastened member are in a continuity state.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 18, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Koji DEMIZU
  • Patent number: 10172264
    Abstract: A housing includes a first member that has a first conductor, a second member that has a second conductor and cooperates with the first member to accommodate a circuit board on which an electronic element is mounted, inside a space surrounded by the first conductor and the second conductor, and a plurality of connecting elements that are arranged at a predetermined arrangement interval y to fix the second member to the first member.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Kai Nojima, Kenji Nagase, Yoshinori Mesaki
  • Publication number: 20180276329
    Abstract: A non-transitory, computer-readable recording medium having stored therein a program for causing a computer to execute a process that includes: setting a starting point and a target component on a circuit of a circuit diagram; tracing lines based on connection relationship of a component located between the starting point and the target component; counting the number of lines between the starting point and the target component; determining positional relationship of components based on the counted number of the lines; and outputting information that the positional relationship is inappropriate when determination result indicates that the positional relationship is inappropriate.
    Type: Application
    Filed: February 23, 2018
    Publication date: September 27, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki HIRATSUKA, Kazunori KASUGA, Tomoyuki NAKAO, Kenji NAGASE
  • Publication number: 20180150591
    Abstract: A coupling distance y of a plurality of securing elements for coupling two members to construct a casing for accommodating a circuit board having electric components mounted thereon inside space surrounded by a conductor extracted from design data, an overlapping width x of overlap sections provided to the two members for coupling the two members with the plurality of securing elements, the overlap sections contacting to each other, and a wavelength ? of electromagnetic noises generated from the electric components, are extracted. Then, a recommended coupling distance Y for the plurality of securing elements to attenuate the electromagnetic noises by a certain attenuation amount is calculated, based on the overlapping width x and the wavelength ?, and the coupling distance y is compared with the recommended coupling distance Y. Thereby, verifications of an electromagnetic noise countermeasure can be made reliably without relying on settings by a user.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Kai Nojima, Kenji NAGASE, YOSHINORI MESAKI
  • Publication number: 20180027707
    Abstract: A housing includes a first member that has a first conductor, a second member that has a second conductor and cooperates with the first member to accommodate a circuit board on which an electronic element is mounted, inside a space surrounded by the first conductor and the second conductor, and a plurality of connecting elements that are arranged at a predetermined arrangement interval y to fix the second member to the first member.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 25, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Kai Nojima, Kenji NAGASE, Yoshinori MESAKI
  • Patent number: 9713262
    Abstract: A via adding method comprising: identifying a target area where a via is to be added in a printed circuit board; determining a starting point for starting a search for a location of the via in the target area; and moving a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and determining whether the via is to be added at a moved search point.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 18, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Nagase, Yoshiaki Hiratsuka, Tomoyuki Nakao, Yoshihiro Sawada, Keisuke Nakamura
  • Patent number: 9507905
    Abstract: A non-transitory recording medium storing a program that causes a computer to execute a circuit board design assistance process. The circuit board design assistance process includes: extracting, from design information of a multilayer circuit board in which a plurality of layers are layered, a plurality of ground patterns in the multilayer circuit board that are within a predetermined distance from a path of a signal that flows in the multilayer circuit board; resolving a region at which the plurality of ground patterns are electronically separated as being a discontinuity region; and displaying the resolved discontinuity region.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Kenji Nagase, Tomoyuki Nakao, Yoshihiro Sawada, Keisuke Nakamura
  • Publication number: 20160007471
    Abstract: A via adding method comprising: identifying a target area where a via is to be added in a printed circuit board; determining a starting point for starting a search for a location of the via in the target area; and moving a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and determining whether the via is to be added at a moved search point.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Kenji NAGASE, Yoshiaki HIRATSUKA, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Patent number: 9173295
    Abstract: A design support apparatus includes: an area identifying unit configured to identify a target area where a via is to be added in a printed circuit board; a determining unit configured to determine a starting point for starting a search for a location of the via in the target area; and a searching unit configured to move a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and to determine whether the via is to be added at a moved search point.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 27, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Nagase, Yoshiaki Hiratsuka, Tomoyuki Nakao, Yoshihiro Sawada, Keisuke Nakamura
  • Publication number: 20150278422
    Abstract: A non-transitory recording medium storing a program that causes a computer to execute a circuit board design assistance process. The circuit board design assistance process includes: extracting, from design information of a multilayer circuit board in which a plurality of layers are layered, a plurality of ground patterns in the multilayer circuit board that are within a predetermined distance from a path of a signal that flows in the multilayer circuit board; resolving a region at which the plurality of ground patterns are electronically separated as being a discontinuity region; and displaying the resolved discontinuity region.
    Type: Application
    Filed: February 2, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki HIRATSUKA, Kenji NAGASE, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Patent number: 8850376
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Nakao, Yoshiaki Hiratsuka, Keisuke Nakamura, Yoshihiro Sawada, Kenji Nagase
  • Publication number: 20140284093
    Abstract: A design support apparatus includes: an area identifying unit configured to identify a target area where a via is to be added in a printed circuit board; a determining unit configured to determine a starting point for starting a search for a location of the via in the target area; and a searching unit configured to move a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and to determine whether the via is to be added at a moved search point.
    Type: Application
    Filed: November 12, 2013
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kenji NAGASE, Yoshiaki HIRATSUKA, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Publication number: 20130326452
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets.
    Type: Application
    Filed: March 25, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki NAKAO, Yoshiaki HIRATSUKA, Keisuke NAKAMURA, Yoshihiro SAWADA, Kenji NAGASE
  • Patent number: 8584076
    Abstract: A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Nagase, Yoshihiro Sawada, Yoshiaki Hiratsuka, Tomoyuki Nakao, Keisuke Nakamura