Abstract: A plurality of tester channels is provided. The tester channels are capable of outputting double speed test patterns when a pin-multiplex-mode is designated. Each of the tester channels is provided with a level determination unit to output a level determination signal, a signal multiplexing unit, and an expected value comparison unit to receive an output from the signal multiplexing unit. The signal multiplexing unit multiplexes an outputted level determination signal obtained in one of the tester channels and a level determination signal obtained from a level determination unit of another one of the tester channels when a double speed test mode is designated. The signal multiplexing unit outputs a signal corresponding to the level determination signal of the one of the tester channels when the double speed test mode is canceled. A strobe time can be set individually for each of the tester channels to obtain a comparison result.

Abstract: In test program generation system and test program generation method for semiconductor test apparatus, there is used data necessary for generation of test programs of respective kinds of LSI testers of data of library in which information common to respective kinds of LSI testers are registered, and data of device information file in which inherent device information are registered every kinds of LSIs to convert those data into data of common language independent of inherent various test program languages every kinds of LSI testers to thereby generate test element data used for generation of test programs of respective kinds of LSI testers. Accordingly, preparation of test programs corresponding to respective kinds of LSI testers can be made. Thus, it becomes possible to easily carry out preparation and modification of template files in which measurement sequences prepared every kinds of LSI testers are described.

Abstract: In the pattern generating apparatus, various instruction codes can be generalized, so that various test patterns of different formats prepared for various testers (semiconductor test apparatus) of different models can be used in common. The pattern generating apparatus comprises: an address pointer (2) for applying a memory address (3) to an instruction memory (1); a plurality of decoders (41, 42) selected by two decode enable signals (22, 23) for generating instruction elements (5) on the basis of the instruction code (1-m) outputted by the instruction memory (1); an address generating section (6) for generating a branch destination address (7) on the basis of the instruction elements (65) outputted by the decoder (41 or 42) and for setting the generated branch destination address (7) to the address pointer (2). One of the decoders (41, 42) is selected on the basis of the decode enable signals (22, 23), and the selected decoder generates the instruction elements (5) of plural tester models.