Abstract: In a pulse duty ratio discrimination circuit for discriminating duty ratios of input signals by comparing a count value with a threshold value through means of counting, with a counter using clocks, a time period starting with a reference level changing point occurring every predetermined period in the input signal and ending with a level returning point, the present invention is characterized by a pulse duty ratio discrimination circuit that includes not only period determination means for determining the periods of the input signals by resetting the count value of the counter at the period of the input signal and by comparing actual count values for a plural number of count patterns of the counter established in advance, but also clock selection means for selecting the frequency of the clock based on a determination result of the period determination means.

Abstract: A digital comb filter includes a period measurement circuit, a subtracter, a first adder, a first memory and a first multiplier. The period measurement circuit outputs difference signals representing differences between periods of target and input pulses. The subtracter subtracts a first deviation signal of the first multiplier from the difference signal of the period measurement circuit. The first adder adds a first accumulation signal of the first memory to the output of the subtracter. The first memory latches the output of the first adder, and the first multiplier multiplies the first accumulation signal by a first coefficient. The digital comb filter also includes a second adder, a second memory, a second multiplier and a third adder. The second adder adds a second accumulation signal of the second memory to the output of the first adder. The second memory latches the output of the second adder.

Abstract: In a tracking control apparatus using a microcomputer, a speed signal proportional to the rotating speed of a capstan motor is generated by an FG coil and applied to a CPU and a latch in the microcomputer. Time data generated by a time counter is held by the latch every time the speed signal is generated. The CPU calculates the rotation frequency of the capstan motor in accordance with the interval of time of generation of the speed signal based on the time data. When a reference signal generated by a reference signal generator and a control signal reproduced by a control head are applied to the CPU, each time data therefor is held by a separate latch. The CPU thus calculates a phase error of the capstan motor in accordance with the difference in the time data for the reference and control signals. The CPU further calculates control data from the rotation frequency and phase error of the capstan motor. The level of a video signal reproduced by a video head is detected by a peak detector.

Abstract: A speed detector outputs a deviation, from a desired rotation speed, of the rotation speed of a capstan motor for driving a tape. A phase detector outputs a phase deviation, from a reference signal, of a reproduction control signal. When in a recording mode, in which only speed control is effected, the capstan motor is driven on the basis of a signal obtained by integrating the integration output of the speed detector. When in a reproduction mode, in which speed and phase controls are effected, the capstan motor is driven on the basis of a signal obtained by adding the deviation output of the speed detector to a signal derived by integrating the deviation output of the phase detector. Further, the capstan motor is driven on the basis of the integration data, which is stored in a data register in the reproduction mode, at the time of transition from the reproduction mode to the recording mode.