Abstract: Values of control signals 61, 62, 63, . . . , 6n, each inputted to an input terminal for operation control 6 of each of transistor elements 4 constituting a variable resistance portion 2, are controlled based upon an input signal 40 and offset signals 52, 53, . . . , 5n generated by an offset provision portion 3. Thus, a ratio of the maximum resistance value to the minimum resistance value can be made large, while using a limited power supply voltage range as a control range.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: The output amplitude of a variable gain amplifier is compared with a reference value by a differential amplifier. When the amplitude is less than the reference value, the gain of the variable gain amplifier is increased to augment the output amplitude. When the amplitude is greater than the reference value, the gain of the variable gain amplifier is decreased to reduce the output amplitude. Only part of the variable gain range of the variable gain amplifier is corresponded to the potential at VLP by installing an input switching unit for inverting the output polarity of the differential amplifier, an input switching unit for inverting the output polarity of a differential amplifier, comparator, an IDAC, and a logic circuit for controlling the ON and OFF of switches of the input switching units and the output current value of the IDAC.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: Values of control signals 61, 62, 63, . . . , 6n, each inputted to an input terminal for operation control 6 of each of transistor elements 4 constituting a variable resistance portion 2, are controlled based upon an input signal 40 and offset signals 52, 53, . . . , 5n generated by an offset provision portion 3. Thus, a ratio of the maximum resistance value to the minimum resistance value can be made large, while using a limited power supply voltage range as a control range.

Abstract: The output amplitude of a variable gain amplifier is compared with a reference value by a differential amplifier. When the amplitude is less than the reference value, the gain of the variable gain amplifier is increased to augment the output amplitude. When the amplitude is greater than the reference value, the gain of the variable gain amplifier is decreased to reduce the output amplitude. Only part of the variable gain range of the variable gain amplifier is corresponded to the potential at VLP by installing an input switching unit for inverting the output polarity of the differential amplifier, an input switching unit for inverting the output polarity of a differential amplifier, comparator, an IDAC, and a logic circuit for controlling the ON and OFF of switches of the input switching units and the output current value of the IDAC.