Patents by Inventor Yoshiaki Masuda
Yoshiaki Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240383035Abstract: One aspect of the present invention is a method for manufacturing an electronic component, the method including: a first step of applying a metal paste containing metal particles onto a polymer compact in a prescribed pattern to form a metal paste layer; a second step of sintering the metal particles to form metal wiring; a third step of applying a solder paste containing solder particles and a resin component onto the metal wiring to form a solder paste layer; a fourth step of disposing an electronic element on the solder paste layer; and a fifth step of heating the solder paste layer so as to form a solder layer bonding the metal wiring and the electronic element, and so as to form a resin layer covering at least a portion of the solder layer.Type: ApplicationFiled: July 12, 2024Publication date: November 21, 2024Applicant: RESONAC CORPORATIONInventors: Yoshinori EJIRI, Shinichirou SUKATA, Masaya TOBA, Hideo NAKAKO, Yuki KAWANA, Kosuke URASHIMA, Motoki YONEKURA, Takaaki NOHDOH, Yoshiaki KURIHARA, Hiroshi MASUDA, Keita SONE
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Publication number: 20240363656Abstract: The present disclosure relates to an imaging element package and an electronic device that allow images to be captured with better quality. A support portion configured to support a cover glass that protects a light-receiving surface of a semiconductor substrate provided with a photodiode is provided along an outer periphery of the semiconductor substrate, and an antireflection layer is provided between the support portion and the semiconductor substrate at least in an area where the support portion is provided. The antireflection layer is provided entirely on the light-receiving surface of the semiconductor substrate, and the support portion is stacked on the antireflection layer. The present disclosure can be applied to a CMOS image sensor, for example.Type: ApplicationFiled: May 23, 2022Publication date: October 31, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Takashi MIYANAGA, Koshi OKITA, Shinichiro NOUDO, Shingo HAMAGUCHI, Atsushi TODA, Tomohiko ASATSUMA, Naoki YAMASHITA
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Publication number: 20240306490Abstract: Compounds of formulae (2-7) or (2-9) are provided: Also provided are organic electroluminescence (EL) devices containing the compounds having a high emission efficiency when operated at low voltage and a long lifetime and electronic devices including such organic EL devices.Type: ApplicationFiled: April 25, 2024Publication date: September 12, 2024Applicant: IDEMITSU KOSAN CO.,LTD.Inventors: Ryota TAKAHASHI, Tomoki KATO, Hirokatsu ITO, Masahiro KAWAMURA, Masakazu FUNAHASHI, Hiroyuki SAITO, Yuichiro KAWAMURA, Yoshiaki TAKAHASHI, Tetsuya MASUDA, Hitoshi KUMA
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Publication number: 20240290801Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.Type: ApplicationFiled: April 5, 2024Publication date: August 29, 2024Applicant: SONY GROUP CORPORATIONInventors: Harumi TANAKA, Yoshiaki MASUDA, Shinji MIYAZAWA, Minoru ISHIDA
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Patent number: 12070800Abstract: One aspect of the present invention is a method for manufacturing an electronic component, the method including: a first step of applying a metal paste containing metal particles onto a polymer compact in a prescribed pattern to form a metal paste layer; a second step of sintering the metal particles to form metal wiring; a third step of applying a solder paste containing solder particles and a resin component onto the metal wiring to form a solder paste layer; a fourth step of disposing an electronic element on the solder paste layer; and a fifth step of heating the solder paste layer so as to form a solder layer bonding the metal wiring and the electronic element, and so as to form a resin layer covering at least a portion of the solder layer.Type: GrantFiled: September 5, 2019Date of Patent: August 27, 2024Assignee: RESONAC CORPORATIONInventors: Yoshinori Ejiri, Shinichirou Sukata, Masaya Toba, Hideo Nakako, Yuki Kawana, Kosuke Urashima, Motoki Yonekura, Takaaki Nohdoh, Yoshiaki Kurihara, Hiroshi Masuda, Keita Sone
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Publication number: 20240209027Abstract: The present invention relates to a peptide and a composition comprising the peptide. This peptide of the present invention comprises the following amino acid sequence: MeA-MeF-S-Cha-Y-S-Y-Y-R-R-Cha-C (SEQ ID NO: 2) or an amino acid sequence having a substitution, addition, deletion, or insertion in 1 to 10 amino acid residues selected from the group consisting of amino acid residues at positions 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 in the above amino acid sequence.Type: ApplicationFiled: March 22, 2022Publication date: June 27, 2024Inventors: Koichi Watashi, Hirofumi Ohashi, Keiichi Masuya, Masaki Ohuchi, Haruaki Kurasaki, Katsuma Matsui, Takayuki Nagasawa, Junpei Yamamoto, Kazutaka Nagatomo, Kei Sudo, Naoko Nakamura, Koji Yoshida, Yoshiaki Shimada, Tatsuya Niimi, Yoshiaki Masuda, Naoko Iwata, Nozomi Shiwa, Noriyo Nagata, Tadaki Suzuki, Hidetomo Kitamura
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Patent number: 12009382Abstract: There is provided an imaging device capable of further improving image quality of a subject, particularly a lesion portion such as cancer. There is provided an imaging device including: a first substrate including a first pixel array unit in which a plurality of pixels having at least a first photoelectric conversion unit is arranged in a two-dimensional manner, a first wiring layer, and a first support layer stacked in this order; and a second substrate including a second pixel array unit in which a plurality of pixels having at least a second photoelectric conversion unit is arranged in a two-dimensional manner, a second wiring layer, and a second support layer stacked in this order, in which the first support layer and the second support layer are bonded to each other to form a stacked structure, and at least one of the support layers includes an antireflection layer.Type: GrantFiled: December 19, 2019Date of Patent: June 11, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Tomohiko Asatsuma
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Publication number: 20240186352Abstract: Provided is an imaging device capable of suppressing an influence of flare. An imaging device according to the present disclosure includes: a pixel region in which a plurality of pixels that performs photoelectric conversion is arranged; an on-chip lens provided on the pixel region; a protective member provided on the on-chip lens; and a resin layer that adheres between the on-chip lens and the protective member, in which when a thickness of the resin layer and the protective member is T, a length of a diagonal line of the pixel region viewed from an incident direction of light is L, and a critical angle of the protective member is ?c, T?L/2/tan?c (Formula 2) or T?L/4/tan?c (Formula 3) is satisfied.Type: ApplicationFiled: February 9, 2022Publication date: June 6, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Keisuke HATANO, Hirokazu SEKI, Atsushi TODA, Shinichiro NOUDO, Yusuke OIKE, Yutaka OOKA, Naoto SASAKI, Toshiki SAKAMOTO, Takafumi MORIKAWA
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Patent number: 11973091Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.Type: GrantFiled: January 13, 2021Date of Patent: April 30, 2024Assignee: Sony CorporationInventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida
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Patent number: 11923395Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.Type: GrantFiled: May 13, 2021Date of Patent: March 5, 2024Assignee: Sony Group CorporationInventors: Yoshiaki Masuda, Minoru Ishida
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Publication number: 20230335574Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Tokihisa KANEGUCHI
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Patent number: 11735615Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: GrantFiled: May 14, 2019Date of Patent: August 22, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Tokihisa Kaneguchi
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Publication number: 20230253427Abstract: The present technology relates to a semiconductor package and a method for manufacturing the semiconductor package that are capable of improving the quality of the semiconductor package having a WCSP structure. A semiconductor package includes: a semiconductor substrate including a light receiving element; an on-chip lens disposed on an incident surface side of the semiconductor substrate; a resin layer in contact with a central portion including a most protruding portion of the on-chip lens; and a glass substrate in contact with a surface of the resin layer opposite to a surface of the resin layer in contact with the on-chip lens, wherein a space is provided between a peripheral portion around the central portion of the on-chip lens and the resin layer. The present technology can be applied to, for example, an imaging element.Type: ApplicationFiled: June 23, 2021Publication date: August 10, 2023Inventors: YOSHIAKI MASUDA, TOKIHISA KANEGUCHI
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Publication number: 20230230986Abstract: A solid-state imaging element according to the present disclosure includes a first light receiving pixel, a second light receiving pixel, and a metal layer. The first light receiving pixel receives visible light. The second light receiving pixel receives infrared light. The metal layer is provided to face at least one of a photoelectric conversion unit of the first light receiving pixel and a photoelectric conversion unit of the second light receiving pixel on an opposite side of a light incident side, and contains tungsten as a main component.Type: ApplicationFiled: April 14, 2021Publication date: July 20, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Kazuyoshi YAMASHITA, Shinichiro KURIHARA, Syogo KUROGI, Yusuke UESAKA, Toshiki SAKAMOTO, Hiroyuki KAWANO, Masatoshi IWAMOTO, Takashi TERADA, Sintaro NAKAJIKI, Shinta KOBAYASHI, Chihiro ARAI
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Publication number: 20230215901Abstract: A solid-state imaging element that includes a semiconductor layer, a floating diffusion region (FD), a penetrating pixel separation region, and a non-penetrating pixel separation region. In the semiconductor layer, a visible-light pixel (PDc) that receives visible light and an infrared-light pixel (PDw) that receives infrared light are two-dimensionally arranged. The floating diffusion region is provided in the semiconductor layer and is shared by adjacent visible-light and infrared-light pixels. The penetrating pixel separation region is provided in a region excluding a region corresponding to the floating diffusion region in an inter-pixel region of the visible-light pixel and the infrared-light pixel, and penetrates the semiconductor layer in a depth direction.Type: ApplicationFiled: April 12, 2021Publication date: July 6, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuyoshi YAMASHITA, Yoshiaki MASUDA, Shinichiro KURIHARA, Syogo KUROGI, Yusuke UESAKA, Toshiki SAKAMOTO, Hiroyuki KAWANO, Masatoshi IWAMOTO, Takashi TERADA, Sintaro NAKAJIKI
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Publication number: 20230197748Abstract: The solid-state imaging element includes a plurality of first light receiving pixels that receives visible light, a plurality of second light receiving pixels that receives infrared light, a separation region, and a light shielding wall. The plurality of first light receiving pixels and the plurality of second light receiving pixels are arranged in a matrix, and the separation regionis arranged in a lattice pattern, light and has a plurality of intersection portions The light shielding wall is provided in the separation region and includes a first light shielding wall provided along a first direction in plan view, and a second light shielding wall provided along a second direction intersecting the first direction in plan view. In addition, the first light shielding wall and the second light shielding wall are spaced apart at the intersection portionof at least a part of the separation region.Type: ApplicationFiled: April 13, 2021Publication date: June 22, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke UESAKA, Kazuyoshi YAMASHITA, Yoshiaki MASUDA, Shinichiro KURIHARA, Syogo KUROGI, Toshiki SAKAMOTO, Hiroyuki KAWANO, Masatoshi IWAMOTO, Takashi TERADA, Sintaro NAKAJIKI
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Publication number: 20230063356Abstract: There is provided a biological substance detection chip having high detection accuracy. The present technology provides a biological substance detection chip which is composed of a plurality of pixels, in which the pixel includes a holding surface on which a biological substance is held, a photoelectric conversion unit that is provided below the holding surface and provided on a semiconductor substrate, and a wiring layer that is provided below the photoelectric conversion unit.Type: ApplicationFiled: January 29, 2021Publication date: March 2, 2023Inventors: HARUMI TANAKA, YOSHIAKI MASUDA, YUSUKE UESAKA, TAKAFUMI MORIKAWA
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Publication number: 20230057090Abstract: Provided is a solid-state imaging device capable of improving sensitivity of near-infrared wavelengths and suppressing color mixing without being restricted by a wiring layout. A solid-state imaging device includes: a substrate on which a plurality of photoelectric conversion units are formed corresponding to different light wavelengths; a wiring layer including a transistor on a surface opposite to a surface on a light incident side of the substrate and on a photoelectric conversion unit side to execute signal processing on a charge output from the photoelectric conversion unit and a wiring on a side opposite to the photoelectric conversion unit side of the transistor so as to transfer an electrical signal obtained by the transistor; and a reflection design film on a transistor side from at least a junction between the substrate and the wiring layer, which has higher reflectivity than the wiring layer and reflects a vertical component of incident light.Type: ApplicationFiled: January 7, 2021Publication date: February 23, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yoshiaki MASUDA
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Publication number: 20230055685Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable further downsizing of device size. The device includes: a first structural body and a second structural body that are layered, the first structural body including a pixel array unit, the second structural body including an input/output circuit unit, and a signal processing circuit; a first through-via, a signal output external terminal, a second through-via, and a signal input external terminal that are arranged below the pixel array, the first through-via penetrating through a semiconductor substrate constituting a part of the second structural body, the second through-via penetrating through the semiconductor substrate; a substrate connected to the signal output external terminal and the signal input external terminal; and a circuit board connected to a first surface of the substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.Type: ApplicationFiled: October 28, 2022Publication date: February 23, 2023Applicant: SONY GROUP CORPORATIONInventors: Shinji MIYAZAWA, Yoshiaki MASUDA
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Publication number: 20230047769Abstract: There is provided a biological substance detection chip having high detection accuracy. The present technology provides a biological substance detection chip which is composed of a plurality of pixels in which the pixel includes at least a holding surface on which a biological substance is held and a photoelectric conversion unit that is provided below the holding surface and provided on a semiconductor substrate, wherein a partition wall made of a conductor is provided between the pixels on the holding surface. In addition, the present technology provides a biological substance detection device and a biological substance detection system using the biological substance detection chip.Type: ApplicationFiled: January 29, 2021Publication date: February 16, 2023Inventors: HARUMI TANAKA, YOSHIAKI MASUDA