Patents by Inventor Yoshiaki Minoya

Yoshiaki Minoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9779608
    Abstract: An alarm output circuit can cope with simultaneous generations of a plurality of alarm factors based on alarm signals output from one output terminal. The alarm output circuit notifies externally of generations of alarm factors in an intelligent power module. A digital/analog converter, into which digital data indicating the presences and absences of generations of the alarm factors is input, outputs corresponding voltages. A voltage control oscillator outputs a signal of a frequency corresponding to an output voltage of the digital/analog converter.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 3, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Minoya
  • Patent number: 9587616
    Abstract: An internal combustion engine ignition device can determine ignition timing with high precision to perform ignition with high precision even where noise superimposed at the time of rise of current flowing through an ignition coil is generated. In an internal combustion engine ignition device including an output terminal for detecting an internal state such as a coil current, it is possible to prevent generation of pulse noise in the form of chattering at falling and rising edges of a voltage of the output terminal by using a hysteresis comparator, even if noise is superimposed at the time of rise of the coil current. Therefore, a voltage pulse with pulse width of high precision is transmitted to an electronic control unit without the influence of noise, and the ignition timing can be determined properly with high precision.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 7, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Minoya, Takanori Kohama
  • Publication number: 20160005297
    Abstract: An alarm output circuit can cope with simultaneous generations of a plurality of alarm factors based on alarm signals output from one output terminal. The alarm output circuit notifies externally of generations of alarm factors in an intelligent power module. A digital/analog converter, into which digital data indicating the presences and absences of generations of the alarm factors is input, outputs corresponding voltages. A voltage control oscillator outputs a signal of a frequency corresponding to an output voltage of the digital/analog converter.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki MINOYA
  • Publication number: 20150364913
    Abstract: A short circuit detection circuit has an output voltage of a switching device inputted and, when the value of the output voltage becomes lower than a specified threshold value due to an abnormal state such as a load short circuit state, outputs a control signal to a clamping circuit for making the clamping circuit carry out such a clamping operation as to limit the output current of the switching device. When the output voltage rises again by the turning-on operation of the switching device, the change in the output voltage is transmitted onto the output side through a capacitor with following rising in the control signal, by which the rising of the output signal is detected with little delay.
    Type: Application
    Filed: May 11, 2015
    Publication date: December 17, 2015
    Inventor: Yoshiaki MINOYA
  • Patent number: 7723817
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Patent number: 7405913
    Abstract: A semiconductor device in includes a transistor and a surge absorption element such as Zener diode, that are formed on the same substrate and connected in parallel. The surge absorption element has a resistance during breakdown operation that is smaller than the resistance of the surge absorption element during breakdown operation of the transistor. In addition, the secondary breakdown current of the surge absorption element is larger than the secondary breakdown current of the transistor. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the surge absorption element and is limited to a voltage equal to or less than the breakdown voltage of the transistor, which would otherwise be destroyed.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: July 29, 2008
    Assignee: Fuji Electric Device Technology Co.
    Inventors: Hiroshi Tobisaka, Tatsuhiko Fujihira, Shin Kiuchi, Yoshiaki Minoya, Takeshi Ichimura, Naoki Yaezawa, Ryu Saitou, Shouichi Furuhata, Yuichi Harada
  • Publication number: 20070029636
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Application
    Filed: May 29, 2006
    Publication date: February 8, 2007
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Publication number: 20040238893
    Abstract: A semiconductor device for use in includes a base and emitter shorted by means of a surface electrode. The surface electrode of a vertical-type bipolar transistor in which a P-type epitaxial growth layer and a P-type semiconductor substrate form the collector is electrically connected to the drain electrode of a lateral MOSFET by means of a metal electrode wiring. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the vertical-type bipolar transistor and is limited to a voltage equal to or less than the breakdown voltage of the lateral MOSFET that was to be destroyed.
    Type: Application
    Filed: March 15, 2004
    Publication date: December 2, 2004
    Inventors: Hiroshi Tobisaka, Tatsuhiko Fujihira, Shin Kiuchi, Yoshiaki Minoya, Takeshi Ichimura, Naoki Yaezawa, Ryu Saitou, Shouichi Furuhata, Yuichi Harada