Patents by Inventor Yoshiaki Narisawa
Yoshiaki Narisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9922923Abstract: To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a second surface region around the first surface region, and which has a wiring formed thereon. Subsequently, a resist which covers the first surface region is formed. Then, the first surface region and the second surface region are covered with a resin body such that the resist is included therein, and the resist is exposed from the resin body. After that, the exposed resist is removed, so that a resin opening that exposes the base in the first surface region is formed in the resin body.Type: GrantFiled: May 15, 2015Date of Patent: March 20, 2018Assignee: KABUSHIKI KAISHA EASTERNInventor: Yoshiaki Narisawa
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Publication number: 20170148717Abstract: To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a second surface region around the first surface region, and which has a wiring formed thereon. Subsequently, a resist which covers the first surface region is formed. Then, the first surface region and the second surface region are covered with a resin body such that the resist is included therein, and the resist is exposed from the resin body. After that, the exposed resist is removed, so that a resin opening that exposes the base in the first surface region is formed in the resin body.Type: ApplicationFiled: May 15, 2015Publication date: May 25, 2017Applicant: KABUSHIKI KAISHA EASTERNInventor: Yoshiaki NARISAWA
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Patent number: 8841776Abstract: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.Type: GrantFiled: February 25, 2008Date of Patent: September 23, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 8230590Abstract: A method for mounting electronic components includes a step of providing an adhesive on each of plural electronic component mounting parts on a wiring board; and a step of fixing one of the electronic components on each of the plural electronic component mounting parts via the adhesive. When the adhesive is provided on each of the plural electronic component mounting parts, the center of gravity of a volume of the adhesive provided on the mounting part where an Nth electronic component is to be mounted is shifted in a direction closer to the mounting part where an (N minus 1 or greater)th electronic component is provided neighboring and adjacent to the mounting part where the Nth electronic component is to be mounted.Type: GrantFiled: January 3, 2008Date of Patent: July 31, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 8134240Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.Type: GrantFiled: September 11, 2009Date of Patent: March 13, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 7973404Abstract: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay board may be formed at an upper part of the substrate.Type: GrantFiled: March 17, 2006Date of Patent: July 5, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa, Yoshikazu Kumagaya
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Patent number: 7906852Abstract: A semiconductor device, includes a wiring board; a first semiconductor element mounted on the wiring board; a second semiconductor element mounted on the first semiconductor element so that a position of the second semiconductor element is shifted relative to a position of the first semiconductor element; wherein a part of a main surface of the second semiconductor element faces the first semiconductor element; and an electrode pad provided on the main surface of the second semiconductor element is connected to a second semiconductor element connection pad of the wiring board by a connection part.Type: GrantFiled: October 5, 2007Date of Patent: March 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20090321927Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.Type: ApplicationFiled: September 11, 2009Publication date: December 31, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20080196245Abstract: A method for mounting electronic components includes a step of providing an adhesive on each of plural electronic component mounting parts on a wiring board; and a step of fixing one of the electronic components on each of the plural electronic component mounting parts via the adhesive. When the adhesive is provided on each of the plural electronic component mounting parts, the center of gravity of a volume of the adhesive provided on the mounting part where an Nth electronic component is to be mounted is shifted in a direction closer to the mounting part where an (N minus 1 or greater)th electronic component is provided neighboring and adjacent to the mounting part where the Nth electronic component is to be mounted.Type: ApplicationFiled: January 3, 2008Publication date: August 21, 2008Applicant: FUJITSU LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20080150157Abstract: A semiconductor device, includes a wiring board; a first semiconductor element mounted on the wiring board; a second semiconductor element mounted on the first semiconductor element so that a position of the second semiconductor element is shifted relative to a position of the first semiconductor element; wherein a part of a main surface of the second semiconductor element faces the first semiconductor element; and an electrode pad provided on the main surface of the second semiconductor element is connected to a second semiconductor element connection pad of the wiring board by a connection part.Type: ApplicationFiled: October 5, 2007Publication date: June 26, 2008Applicant: FUJITSU LIMITEDInventors: Takao NISHIMURA, Yoshiaki NARISAWA
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Publication number: 20080150120Abstract: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.Type: ApplicationFiled: February 25, 2008Publication date: June 26, 2008Applicant: FUJITSU LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20080023831Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.Type: ApplicationFiled: December 22, 2006Publication date: January 31, 2008Applicant: FUJITSU LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20070132102Abstract: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay board may be formed at an upper part of the substrate.Type: ApplicationFiled: March 17, 2006Publication date: June 14, 2007Applicant: FUJITSU LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa, Yoshikazu Kumagaya