Patents by Inventor Yoshiaki Nozaki

Yoshiaki Nozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220093308
    Abstract: A reactor includes a toroidal coil including a winding wound to have an annular outer shape, a bus bar electrically connected to one end of the winding, and a current sensor that measures electric current flowing through the bus bar. The bus bar includes a crossing passing through a central area including an area inside an internal surface of the annular outer shape and an area in which the area extends along a central axis of the annular outer shape, and the current sensor measures electric current flowing through the crossing.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 24, 2022
    Inventors: Yoshiaki Nozaki, Yasuhiro Ikarashi, Mitsuo Aratono
  • Patent number: 8766275
    Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoyasu Iketani, Tomohiro Nozawa, Yoshiaki Nozaki, John K. Twynam, Hiroshi Kawamura, Keiichi Sakuno
  • Patent number: 8395248
    Abstract: A semiconductor device includes a lead frame 1 having a first lead 6, a second lead 7 and a third lead 8. A power transistor 2 is placed on the first lead 6, and the power transistor 2 is connected to the first lead 6. The power transistor 2 has a drain electrode on one side opposite to a first lead 6 side, and this drain electrode is connected to a Cu chip 3 on the power transistor 2. The Cu chip 3 is connected to the second lead 7 via Al wires 4. As a result, during wire bonding of the Al wires 4, it becomes possible to absorb shocks due to wire bonding by the Cu chip 3, or disperse pressure due to wire bonding by the Cu chip 3, or diffuse heat due to wire bonding by the Cu chip 3.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: March 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiaki Nozaki
  • Publication number: 20120292635
    Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.
    Type: Application
    Filed: December 28, 2010
    Publication date: November 22, 2012
    Inventors: Naoyasu Iketani, Tomohiro Nozawa, Yoshiaki Nozaki, John K. Twynam, Hiroshi Kawamura, Keiichi Sakuno
  • Patent number: 8232580
    Abstract: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as to be on/off-controlled by a control signal from the photodiode.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: July 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiaki Nozaki
  • Publication number: 20100244213
    Abstract: A semiconductor device includes a lead frame 1 having a first lead 6, a second lead 7 and a third lead 8. A power transistor 2 is placed on the first lead 6, and the power transistor 2 is connected to the first lead 6. The power transistor 2 has a drain electrode on one side opposite to a first lead 6 side, and this drain electrode is connected to a Cu chip 3 on the power transistor 2. The Cu chip 3 is connected to the second lead 7 via Al wires 4. As a result, during wire bonding of the Al wires 4, it becomes possible to absorb shocks due to wire bonding by the Cu chip 3, or disperse pressure due to wire bonding by the Cu chip 3, or diffuse heat due to wire bonding by the Cu chip 3.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Inventor: Yoshiaki NOZAKI
  • Patent number: 7733105
    Abstract: In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: June 8, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiaki Nozaki, Hiroshi Kawamura, John Kevin Twynam, Masatomo Hasegawa
  • Publication number: 20080309355
    Abstract: In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 18, 2008
    Inventors: Yoshiaki Nozaki, Hiroshi Kawamura, John Kevin Twynam, Masatomo Hasegawa
  • Publication number: 20080035954
    Abstract: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as to be on/off-controlled by a control signal from the photodiode.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Inventor: Yoshiaki Nozaki
  • Patent number: 7285770
    Abstract: A light is emitted from a light emitting element toward the other surface in a thickness direction of a scanning mirror which can be angularly displaced about an axial line. At least either one of a first light receiving portion and a second light receiving portion receives a light which is emitted from the light emitting element and reflected by a reflecting mirror. The first light receiving portion, the second light receiving portion, and the signal output section produce an electronic signal containing position information which indicates a position which is irradiated with the above-mentioned light. This position information indicates an amount of angular displacement of the scanning mirror. On the basis of this position information, a driving section scans the scanning mirror so that the predetermined irradiation position can be irradiated with a light emitted from a first light source.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: October 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiaki Nozaki, Junichi Nakamura, Shinichi Nakayama
  • Publication number: 20060175544
    Abstract: A light is emitted from a light emitting element toward the other surface in a thickness direction of a scanning mirror which can be angularly displaced about an axial line. At least either one of a first light receiving portion and a second light receiving portion receives a light which is emitted from the light emitting element and reflected by a reflecting mirror. The first light receiving portion, the second light receiving portion, and the signal output section produce an electronic signal containing position information which indicates a position which is irradiated with the above-mentioned light. This position information indicates an amount of angular displacement of the scanning mirror. On the basis of this position information, a driving section scans the scanning mirror so that the predetermined irradiation position can be irradiated with a light emitted from a first light source.
    Type: Application
    Filed: January 12, 2006
    Publication date: August 10, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshiaki Nozaki, Junichi Nakamura, Shinichi Nakayama