Abstract: There is a demand for the development of a novel beverage containing an alternative sweetener to sugar. The present invention provides a beverage containing 0.1-25 w/v % of D-arabinose.

Abstract: A work machine includes a motor; an output shaft rotated by the motor, to which a tip tool is attachable; a housing, configured to include an inner case including an accommodation part that accommodates the motor and an outer case located outside the accommodation part; and a base, attachable to and detachable from a mounting surface formed on a side surface of the outer case and having a contact surface able to contact a workpiece, wherein the inner case is provided with a fixing part fixing the outer case, and the fixing part is arranged inside the mounting surface in a radial direction of the motor as viewed in an axial direction of the motor.

Abstract: A router includes an illumination part having an LED, and the illumination part is accommodated in an illumination accommodation portion of a holding ring and held by the holding ring. Here, a restriction portion of the holding ring is arranged adjacent to a lower side of a positioning rib of a stator and restricts downward movement of the stator. Thus, the illumination part can be held using the holding ring that restricts the downward movement of the stator. Accordingly, the illumination part can be mounted in the router using a member that holds the illumination part and a member that restricts the downward movement of the stator as a common member.

Abstract: Provided is a router that suppresses a deterioration in stability. In the router 10, a battery holder 60 is provided on the upper side of a motor housing 33, and a battery 70 is detachably attached to the battery holder 60. Therefore, electric power can be supplied from the battery 70 to a motor 40 to drive the motor. Accordingly, convenience can be improved. Here, when viewed from a direction orthogonal to the vertical direction, an angle between a virtual line IL passing through an outer circumferential lower end of a base 20 and the center of gravity G of the router 10 and the lower surface of the base 20 is set to 80 degrees or less.

Abstract: According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.

Abstract: Provided is a power tool capable of suitably fixing an auxiliary member to a base pedestal. The power tool has a base 30 having a sliding surface capable of sliding on a workpiece, and an auxiliary member 60 that is attachable to the base 30 and has a guiding surface 61. The power tool also has a wing bolt 33 and a leaf spring 35 as a pressing mechanism capable of pressing an extension part 62 of the auxiliary member 60. An operator can change a pressing force of the wing bolt 33 to the auxiliary member 60 by changing the position of the wing bolt 33 in a pressing direction. The leaf spring 35 applies a predetermined pressing force to the auxiliary member 60 even in the absence of the pressing force of the wing bolt 33 to the auxiliary member 60.

Abstract: According to one embodiment, a magnetic storage device includes a magnetoresistive element having a first end and a second end. A first switch is between the first end and a first wiring. A second switch is between the second end and a second wiring. A third switch is between the first end and a third wiring. A fourth switch is between the second end and a fourth wiring. A driver is connected to the first wiring and the second wiring and is configured to supply, to the first wiring, a current at a magnitude set based on a voltage at the first end and a voltage at the second end.

Abstract: According to one embodiment, a magnetic storage device includes a magnetoresistive element having a first end and a second end. A first switch is between the first end and a first wiring. A second switch is between the second end and a second wiring. A third switch is between the first end and a third wiring. A fourth switch is between the second end and a fourth wiring. A driver is connected to the first wiring and the second wiring and is configured to supply, to the first wiring, a current at a magnitude set based on a voltage at the first end and a voltage at the second end.

Abstract: According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.

Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.

Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

Abstract: According to one embodiment, a memory system includes: a first memory cell area where a first memory cell is provided; a second memory cell area where a second memory cell is provided; an ECC circuit which corrects an error of data stored by the first memory cell; and a control circuit which replaces the first memory cell with the second memory cell if the number of times an error is successfully corrected in the first memory cell reaches a first value.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.