Patents by Inventor Yoshiaki Ouchi
Yoshiaki Ouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6447355Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 17, 1999Date of Patent: September 10, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
-
Patent number: 6304024Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 17, 1999Date of Patent: October 16, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
-
Patent number: 6034469Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.Type: GrantFiled: December 9, 1997Date of Patent: March 7, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
-
Patent number: 5506804Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: November 30, 1993Date of Patent: April 9, 1996Assignees: Hitachi, Ltd., VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
-
Patent number: 5276648Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: January 8, 1992Date of Patent: January 4, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
-
Patent number: 5177498Abstract: A layer of an amorphous substance containing at least one member from among hydrogen and halogen elements and using as main components thereof silicon and at least one member selected from among nitrogen, carbon, and oxygen is formed as a resin-protecting layer or an abrasion-resistant layer in a thermal printing head or as a resin-protecting layer in a heat-resistant insulating substrate. The hardness of the substrate itself is greatly improved by this layer of the amorphous substance. As the result, the substrate as a whole or the thermal printing head as a whole acquires high rigidity and improved resistance to crack.Type: GrantFiled: December 9, 1991Date of Patent: January 5, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhisa Homma, Masaru Nikaido, Yoshiaki Ouchi, Mutsuki Yamazaki, Shuji Yoshizawa
-
Patent number: 5157107Abstract: A polymeric acid is synthesized by the ring-opening poly-addition reaction using a biphenyl tetracarboxylic acid as a tetracarboxylic acid moiety and an aromatic diamine, particularly p-phenylene diamine, as a diamine moiety. An aromatic polyimide resin layer possessing a highly desirable heat-resisting property as a heat-resistant insulating coating material and excelling in adhesive strength relative to a substrate is obtained by adjusting the polymeric acid in viscosity with a suitable organic solvent, applying the resultant polyamic acid on a substrate, and firing the applied layer of the polyamic acid. The substrate, for example, is a conductor layer formed as with copper and used as a multi-layer wiring board for hybrid IC's.Type: GrantFiled: August 29, 1989Date of Patent: October 20, 1992Assignees: Kabushiki Kaisha Toshiba, Toshiba Chemical CorporationInventors: Masaru Nikaido, Hikaru Okunoyama, Katsumi Yanagibashi, Yoshiaki Ouchi
-
Patent number: 5150325Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: March 20, 1990Date of Patent: September 22, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorpInventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
-
Patent number: 5119112Abstract: A layer of an amorphous substance containing at least one member from among hydrogen and halogen elements and using as main components thereof silicon and at least one member selected from among nitrogen, carbon and oxygen is formed as a resin-protecting layer or an abrasion-resistant layer in a thermal printing head or as a resin-protecting layer in a heat-resistant insulating substrate. The hardness of the substrate itself is greatly improved by this layer of the amorphous substance. As the result, the substrate as a whole or the thermal printing head as a whole acquires high rigidity and improved resistance to crack.Type: GrantFiled: May 4, 1990Date of Patent: June 2, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhisa Homma, Masaru Nikaido, Yoshiaki Ouchi, Mutsuki Yamazaki, Shuji Yoshizawa
-
Patent number: 4963893Abstract: A layer of an amorphous substance containing at least one member from among hydrogen and halogen elements and using as main components thereof silicon and at least one member selected from among nitrogen, carbon, and oxygen is formed as a resin-protecting layer or an abrasion-resistant layer in a thermal printing head or as a resin-protecting layer in a heat-resistant insulating substrate. The hardness of the substrate itself is greatly improved by this layer of the amorphous substance. As the result, the substrate as a whole or the thermal printing head as a whole acquires high rigidity and improved resistance to crack.Type: GrantFiled: March 27, 1989Date of Patent: October 16, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhisa Homma, Masaru Nikaido, Yoshiaki Ouchi, Mutsuki Yamazaki, Shuji Yoshizawa
-
Patent number: 4928034Abstract: According to the present invention, an impregnated cathode is provided wherein an alloy layer of iridium and tungsten is formed on a surface of a porous pellet impregnated with an oxide of an alkali earth metal, wherein a crystal structure of the alloy has an .epsilon.II phase comprising an hcp structure whose lattice constants a and c satisfy 2.76.ltoreq.a.ltoreq.2.78 and 4.44.ltoreq.c.ltoreq.4.46, respectively. The impregnated cathode of the present invention maintains stable electron emission characteristics from an early stage of operation.Type: GrantFiled: November 18, 1988Date of Patent: May 22, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Sakae Kimura, Masaru Nikaido, Katumi Yanagibashi, Katsuhisa Homma, Yoshiaki Ouchi
-
Patent number: 4923763Abstract: There are disclosed a perpendicular magnetic recording medium comprising a substrate of a polymer film containing 0.7% by weight or less of a residual solvent and a ferromagnetic alloy layer formed on the substrate and a method for preparing the same comprising the steps of heating a substrate composed of a polymer film containing a residual solvent in order to regulate a content of the solvent existing in the substrate to 0.7% by weight or less; and afterward forming a magnetic layer composed of a ferromagnetic alloy on the substrate.The perpendicular magnetic recording medium of the present invention has a prolonged durability and heightened reliability.Type: GrantFiled: September 19, 1988Date of Patent: May 8, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Nakamura, Takashi Yamada, Yoshiaki Ouchi
-
Patent number: 4906893Abstract: An output phosphor film used in an output screen of an image intensifier is made of ZnS or (Zn, Cd)S host material and at least one activator element selected from the group consisting of Cu, Ag, Au, Al, and Cl. The phosphor film is formed on a face plate by means of chemical vapor-deposition, or physical vapor deposition in an inert-gas atmosphere having a pressure of 1 Pa or more, and is heat-treated. The formed phosphor film has hexagonal (Wurtzite-type) crystal and/or cubic (sphalerite-type) crystal structure. These crystals are orientated such that the (002) planes of the hexagonal crystals and/or the (111) planes of the cubic crystals are substantially parallel to the face plate.Type: GrantFiled: December 20, 1988Date of Patent: March 6, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhisa Homma, Sakae Kimura, Masaru Nikaido, Yoshiaki Ouchi, Yoshiharu Obata, Yoshikazu Uemura, Syozo Sato
-
Patent number: 4868584Abstract: A polyamic acid is synthesized by the ring-opening poly-addition reaction using a biphenyl tetracarboxylic acid as a tetracarboxylic acid moiety and an aromatic diamine, particularly p-phenylene diamine, as a diamine moiety. An aromatic polyimide resin layer possessing a highly desirable heat-resisting property as a heat-resistant insulating coating material and excelling in adhesive strength relative to a substrate is obtained by adjusting the polyamic acid in viscosity with a suitable organic solvent, applying the resultant polyamic acid on a substrate, and firing the applied layer of the polyamic acid. The substrate, for example, is a conductor layer formed as with copper and used as a multi-layer wiring board for hybrid IC's.Type: GrantFiled: January 29, 1988Date of Patent: September 19, 1989Assignees: Kabushiki Kaisha Toshiba, Toshiba Chemical CorporationInventors: Masaru Nikaido, Hikaru Okunoyama, Katsumi Yanagibashi, Yoshiaki Ouchi
-
Patent number: 4835548Abstract: In a thermal head, an electrical and heat insulating layer of glass is formed on a substrate made of ferrie Fe-Cr stainless steel. Fe-Cr stainless steel contains 16 to 18% chromium by weight. Heating resistors having a specific patterns are formed on the electrical and heat insulating layer and electrically connected to the substrate acting as a common electrode. Lead wires of an A.lambda.-Si-Cu alloy, as individual electrodes, are formed on the layer and the heating resistors. The heating resistors and the lead wires are covered by a protective layer.Type: GrantFiled: June 17, 1987Date of Patent: May 30, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Nikadio, Yoshiaki Ouchi, Tadayoshi Kinoshita, Reiko Watanabe, Shinzo Sugai
-
Patent number: 4760370Abstract: A resistor is provided which comprises an insulation substrate, a resistive layer prepared from inorganic materials and printed on the insulation substrate, and an insulation layer prepared from borosilicate lead glass and overcoated on the resistive layer. The insulation layer contains an oxide of at least one transition metal selected from the group consisting of iron, nickel, chromium, cobalt, zinc, copper, zirconium, and cadmium. In the course of operation, the resistor of the present invention exhibits no changes in its resistance, irrespective of the length of time it may be operated.Type: GrantFiled: June 25, 1987Date of Patent: July 26, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Nikaido, Yoshiaki Ouchi, Taketoshi Shimoma, Eiji Kamohara, Shigeru Sugawara, Hideki Yamaguchi
-
Patent number: 4562555Abstract: An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential.Type: GrantFiled: September 23, 1983Date of Patent: December 31, 1985Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Yoshiaki Ouchi, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa