Patents by Inventor Yoshiaki Saka

Yoshiaki Saka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6704371
    Abstract: A low noise and lower power consumption receiver including a CRC error correction circuit which is constructed at low cost, prolongs a life of a battery and enhances a receiving sensitivity. The receiver comprises a data processing unit which continuously determines errors in received data encoded by a CRC code and corrects them by comparing with reference syndrome patterns, a microprocessor circuit including a data RAM connected with local data buses and local address buses and a serial data receiving apparatus including state control means, a synchronizing circuit, an ID comparing circuit and a circuit for gating system clock. The high performance and low power consumption receiver may be realized with less additional circuits, having more flexibility to the increase of services.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: March 9, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yuji Hishiki, Isamu Fujii, Yoshiaki Saka, Shinichi Idomukai
  • Patent number: 5760699
    Abstract: In a selected paging signal type receiving apparatus, a transmission code is received which is arranged by coupling a series of signal codes including a preamble, a sync code, and a message code. Even when signal reception is interrupted, this receiving apparatus can immediately respond to an interference condition and a completion of a signal transmission. In the case of the interference condition, the receiving apparatus can be immediately recovered to the signal reception operation after the interference condition disappears.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: June 2, 1998
    Assignee: Seiko Instruments, Inc.
    Inventors: Yoshiaki Saka, Shinichi Idomukai, Isamu Fujii, Yuji Hishiki
  • Patent number: 5557772
    Abstract: A microinstruction memory stores microinstructions, and a microinstruction execution unit executes a selected one of the microinstructions by a pipeline process and outputs an operation result. The microinstructions include a specific microinstruction. The data processing apparatus also includes a correction part which has the microinstruction execution unit execute the specific microinstruction when a predetermined event occurs so that the parameter is changed to a corrected parameter which corresponds to a parameter used in an immediately previous pipeline process. The microinstruction execution unit stops operating when the predetermined event occurs and starts the operation again by using the corrected parameter.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: September 17, 1996
    Assignee: Fujitsu Limited
    Inventors: Yoshiaki Saka, Toshiharu Ohshima