Abstract: Provided is a semiconductor module comprising a semiconductor chip, a lead frame including a chip connection portion configured to connect the lead frame to the semiconductor chip, and a bonding member configured to connect the chip connection portion and the semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, an active portion provided on the semiconductor substrate, and a transverse protective film provided above the active portion and provided to traverse the active portion in a top view, wherein the chip connection portion includes a center portion which covers a center of the transverse protective film in a top view and a first cut-out portion provided from a first end side of the chip connection portion towards the center portion.

Abstract: [Problem] To provide a method for further reducing the friction resistance of a friction resistance reduced ship. [Solution] Rolling and pitching vary greatly depending on variations in climate, etc.; however, when limited to an extremely short time, the rolling and pitching repeat in an almost identical or similar pattern. Therefore, if the pattern of the immediately preceding rolling and pitching is understood, the subsequent pattern can also be predicted. This is similar for vertical position variation patterns of minute bubble generation units calculated from the angle of the rolling and pitching. Furthermore, the vertical position variation also differs depending on the installation position of each minute bubble generation unit, so the present invention measures the vertical position variation for each minute bubble generation unit, while also predicting the vertical position variation at and after the current time.

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

Abstract: A dry vacuum pump regeneration apparatus includes an intake pipe connected to an intake port of a dry vacuum pump; an exhaust pipe connected to an exhaust port of the dry vacuum pump; an auxiliary vacuum pump configured to evacuate an interior of the dry vacuum pump upon being stopped via the exhaust pipe; a plasma generator configured to cause a first gas to pass through the plasma generator to generate a plasma in an atmosphere of the passing first gas, and release a radical of the first gas to the intake port via the intake pipe; a first gas heating device configured to cause a second gas to pass through the first gas heating device, heat the passing second gas, and release the heated second gas to the intake port via the intake pipe; and a bypass pipe connected to the intake pipe and the exhaust pipe.

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

Abstract: A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: The compound represented by formula (1): wherein A, B, R1, and R2 are as defined in the description, provides organic electroluminescence (EL) devices having a high emission efficiency when operated at low voltage and a long lifetime and electronic devices including such organic EL devices.

Abstract: A top emission organic EL device includes an anode, hole transporting zone, emitting layer, electron transporting zone, and cathode in this order. The hole transporting zone includes: a first layer interposed between the anode and the emitting layer; and a second layer interposed between the first layer and the emitting layer. The first layer contains a first compound and the second layer contains a second compound. A film thickness of the first layer and the second layer satisfies a formula (1) and (2), respectively. A hole mobility ?H1 of the first compound satisfies a formula (3) and a hole mobility ?H2 of the second compound satisfies a formula (4), 100 nm?d1?300 nm??(1) 1 nm?d2?20 nm??(2) 1.0×10?4 [cm2/Vs]??H1?1.0×10?1 [cm2/Vs]??(3) 1.0×10?10 [cm2/Vs]??H2?1.0×10?6 [cm2/Vs]??(4).

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

Abstract: The compound represented by formula (1): wherein A, B, R1, and R2 are as defined in the description, provides organic electroluminescence (EL) devices having a high emission efficiency when operated at low voltage and a long lifetime and electronic devices including such organic EL devices.

Abstract: A seal management apparatus for managing an electronic sealing service performs the steps of receiving seal-required data to be used for the sealing service from a user terminal of a user of the sealing service, generating (a) a seal secret key for sealing the seal-required data and (b) a seal public key used for verifying the seal, in a working memory, when the seal-required data is received, registering the seal public key in a blockchain, acquiring a seal identifier that is an identifier for acquiring the seal public key registered in the blockchain from the blockchain, generating a sealed file by affixing a signature of the seal secret key to a file containing the seal-required data and the seal identifier, deleting the seal secret key from the working memory, and transmitting the seal identifier to the user terminal.

Abstract: Provided is a semiconductor module comprising a semiconductor chip, a lead frame including a chip connection portion configured to connect the lead frame to the semiconductor chip, and a bonding member configured to connect the chip connection portion and the semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, an active portion provided on the semiconductor substrate, and a transverse protective film provided above the active portion and provided to traverse the active portion in a top view, wherein the chip connection portion includes a center portion which covers a center of the transverse protective film in a top view and a first cut-out portion provided from a first end side of the chip connection portion towards the center portion.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: A compound represented by the following general formula (I) or a pharmaceutically acceptable salt or solvate thereof, and a pharmaceutical composition thereof, and the use thereof to prevent or treat infectious diseases and a method to prevent or treat infectious diseases using those regimen are disclosed. The compound represented by formula (I) has an antibacterial activity against both gram-positive and gram-negative bacteria, and is useful in the prevention or treatment of infectious diseases caused by these bacteria.

Abstract: A top emission organic EL device includes an anode, hole transporting zone, emitting layer, electron transporting zone, and cathode in this order. The hole transporting zone includes: a first layer interposed between the anode and the emitting layer; and a second layer interposed between the first layer and the emitting layer. The first layer contains a first compound and the second layer contains a second compound. A film thickness of the first layer and the second layer satisfies a formula (1) and (2), respectively. A hole mobility ?H1 of the first compound satisfies a formula (3) and a hole mobility ?H2 of the second compound satisfies a formula (4), 100 nm?d1?300 nm??(1) 1 nm?d2?20 nm??(2) 1.0×10?4 [cm2/Vs]??H1?1.0×10?1 [cm2/Vs]??(3) 1.0×10?10 [cm2/Vs]??H2?1.0×10?6 [cm2/Vs]??(4).

Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Abstract: A compound represented by the following general formula (I) or a pharmaceutically acceptable salt or solvate thereof, and a pharmaceutical composition thereof, and the use thereof to prevent or treat infectious diseases and a method to prevent or treat infectious diseases using those regimen are disclosed. The compound represented by formula (I) has an antibacterial activity against both gram-positive and gram-negative bacteria, and is useful in the prevention or treatment of infectious diseases caused by these bacteria.

Abstract: A compound represented by the following general formula (I) or a pharmaceutically acceptable salt or solvate thereof, and a pharmaceutical composition thereof, and the use thereof to prevent or treat infectious diseases and a method to prevent or treat infectious diseases using those regimen are disclosed. The compound represented by formula (I) has an antibacterial activity against both gram-positive and gram-negative bacteria, and is useful in the prevention or treatment of infectious diseases caused by these bacteria.