Patents by Inventor Yoshiaki Terasaki

Yoshiaki Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134598
    Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Tamio Matsumura, Yoshiaki Terasaki
  • Patent number: 9779951
    Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki, Masatoshi Sunamoto
  • Publication number: 20170200613
    Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).
    Type: Application
    Filed: October 10, 2014
    Publication date: July 13, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazunari NAKATA, Tamio MATSUMURA, Yoshiaki TERASAKI
  • Publication number: 20170076948
    Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.
    Type: Application
    Filed: April 19, 2016
    Publication date: March 16, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazunari NAKATA, Yoshiaki TERASAKI, Masatoshi SUNAMOTO
  • Patent number: 9324581
    Abstract: A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 26, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Patent number: 8993413
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Patent number: 8574962
    Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Publication number: 20130267065
    Abstract: A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.
    Type: Application
    Filed: January 11, 2013
    Publication date: October 10, 2013
    Inventors: Kazunari NAKATA, Yoshiaki TERASAKI
  • Publication number: 20130203241
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
    Type: Application
    Filed: December 7, 2012
    Publication date: August 8, 2013
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Publication number: 20120309117
    Abstract: A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region.
    Type: Application
    Filed: January 26, 2012
    Publication date: December 6, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichiro SUZUKI, Atsushi Narazaki, Yoshiaki Terasaki
  • Publication number: 20120214278
    Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.
    Type: Application
    Filed: September 13, 2011
    Publication date: August 23, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunari NAKATA, Yoshiaki Terasaki