Patents by Inventor Yoshiaki Terasaki
Yoshiaki Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10134598Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).Type: GrantFiled: October 10, 2014Date of Patent: November 20, 2018Assignee: Mitsubishi Electric CorporationInventors: Kazunari Nakata, Tamio Matsumura, Yoshiaki Terasaki
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Patent number: 9779951Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.Type: GrantFiled: April 19, 2016Date of Patent: October 3, 2017Assignee: Mitsubishi Electric CorporationInventors: Kazunari Nakata, Yoshiaki Terasaki, Masatoshi Sunamoto
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Publication number: 20170200613Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).Type: ApplicationFiled: October 10, 2014Publication date: July 13, 2017Applicant: Mitsubishi Electric CorporationInventors: Kazunari NAKATA, Tamio MATSUMURA, Yoshiaki TERASAKI
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Publication number: 20170076948Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.Type: ApplicationFiled: April 19, 2016Publication date: March 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Kazunari NAKATA, Yoshiaki TERASAKI, Masatoshi SUNAMOTO
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Patent number: 9324581Abstract: A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.Type: GrantFiled: January 11, 2013Date of Patent: April 26, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazunari Nakata, Yoshiaki Terasaki
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Patent number: 8993413Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.Type: GrantFiled: December 7, 2012Date of Patent: March 31, 2015Assignee: Mitsubishi Electric CorporationInventors: Kazunari Nakata, Yoshiaki Terasaki
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Patent number: 8574962Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.Type: GrantFiled: September 13, 2011Date of Patent: November 5, 2013Assignee: Mitsubishi Electric CorporationInventors: Kazunari Nakata, Yoshiaki Terasaki
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Publication number: 20130267065Abstract: A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.Type: ApplicationFiled: January 11, 2013Publication date: October 10, 2013Inventors: Kazunari NAKATA, Yoshiaki TERASAKI
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Publication number: 20130203241Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.Type: ApplicationFiled: December 7, 2012Publication date: August 8, 2013Inventors: Kazunari Nakata, Yoshiaki Terasaki
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Publication number: 20120309117Abstract: A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region.Type: ApplicationFiled: January 26, 2012Publication date: December 6, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichiro SUZUKI, Atsushi Narazaki, Yoshiaki Terasaki
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Publication number: 20120214278Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.Type: ApplicationFiled: September 13, 2011Publication date: August 23, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazunari NAKATA, Yoshiaki Terasaki