Patents by Inventor Yoshiaki Toyada

Yoshiaki Toyada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
    Patent number: 9818845
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • MOS-DRIVEN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING MOS-DRIVEN SEMICONDUCTOR DEVICE
    Publication number: 20170092744
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Kin-On SIN, Chun-Wai NG, Hitoshi SUMIDA, Yoshiaki TOYADA, Akihiko OHI, Hiroyuki TANAKA, Takeyoshi NISHIMURA
  • MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
    Patent number: 9553185
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: January 24, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • MOS-DRIVEN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING MOS-DRIVEN SEMICONDUCTOR DEVICE
    Publication number: 20130001681
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Application
    Filed: May 27, 2010
    Publication date: January 3, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura