Abstract: A substrate for use in a semiconductor package is fabricated by preparing a composite metal laminate consisting of a first metal layer, a second metal layer, and a carrier layer positioned in this order. The first metal layer has etching characteristics different to those of the second metal layer with respect to the same etchant. The first metal layer is selectively etched until the second metal layer is exposed, thereby forming pillar-like interconnections. The gap between the interconnections is then filled with a resin so as to form a resin base with interconnections. The carrier layer is removed from the second metal layer, and the second metal layer is selectively etched until the first metal layer or the resin base is exposed, thereby forming a conductive pattern on the resin base.

Abstract: A semiconductor device fabrication process comprising an encapsulation step of carrying out encapsulation by vacuum pressure differential printing by the use of a liquid resin encapsulant containing a solvent in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight. The encapsulation step comprises: printing the liquid resin encapsulant by vacuum pressure differential printing in such a way that; the encapsulant covers at least an internal connecting terminal provided on a substrate, a semiconductor chip, and a wire interconnecting the internal connecting terminal and the semiconductor chip; and that the thickness of the encapsulant lying above the wire at the highest position of the wire comes to be at least 0.8 times the thickness of the encapsulant lying beneath the wire at the same position; and curing or drying the encapsulant.

Abstract: A substrate for use in a semiconductor package is fabricated by preparing a composite metal laminate consisting of a first metal layer, a second metal layer, and a carrier layer positioned in this order. The first metal layer has etching characteristics different to those of the second metal layer with respect to the same etchant. The first metal layer is selectively etched until the second metal layer is exposed, thereby forming pillar-like interconnections. The gap between the interconnections is then filled with a resin so as to form a resin base with interconnections. The carrier layer is removed from the second metal layer, and the second metal layer is selectively etched until the first metal layer or the resin base is exposed, thereby forming a conductive pattern on the resin base.

Abstract: A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion capable of mounting the semiconductor chip (1) at the center portion of the substrate is formed by press forming with a projected portion (13a) of a die (13) while adhering a press shapeable wiring body comprising a copper wiring (12) which becomes wiring material, a barrier layer (11) such as nickel alloy or the like, and a copper foil (10) which is a carrier layer, to a plastic substrate (14,15), so as to have wiring (2) buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip (1) and an external connection terminal portion connecting to an external connection terminals (5), the internal and external connection terminal portions being two edge portions of the wiring (2).

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: According to the present invention, a tape carrier is prepared which comprises a power trunk line including an electric connection as a branch of a power lead for each tape carrier unit and a ground trunk line having an electric connection as a branch of a ground lead for each tape carrier unit, the power and trunk lines being continuously formed along the longitudinal direction of the tape carrier, and a lead for a control signal for establishing an electric conduction along the longitudinal direction of the tape carrier via an aging wiring for semiconductor pellets to conduct a simultaneous multipoint (gang) bonding on the tape carrier, the control signal lead being formed on the tape carrier.

Abstract: According to the present invention, a tape carrier is prepared which comprises a power trunk line including an electric connection as a branch of a power lead for each tape carrier unit and a ground trunk line having an electric connection as a branch of a ground lead for each tape carrier unit, the power and trunk lines being continuously formed along the longitudinal direction of the tape carrier, and a lead for a control signal for establishing an electric conduction along the longitudinal direction of the tape carrier via an aging wiring for semiconductor pellets to conduct a simultaneous multipoint (gang) bonding on the tape carrier. By mounting the semiconductor pellets having the aging wiring on the tape carrier, it is enabled to apply the power voltage and to supply the control signal to each of the plurality of the semiconductor pellets, and hence the operation test can be simultaneously conducted for the semiconductor pellets mounted on the tape carrier having an arbitrary length.

Abstract: A resin mold type semiconductor device comprising molded articles for sealing, each consisting of a resin material and having a gap portion thereinside; a semiconductor element positioned in said gap portion inside said molded article for sealing, said seminconductor element having electrodes; electrically conductive leads, each positioned in said gap portion of said molded article for sealing and having one end thereof protruding outwardly from said molded article for sealing; wires, each electrically connecting said electrode of said seminconductor element to said lead; and an insulation material covering at least the surface of said semiconductor element.

Abstract: In a semiconductor memory device comprising semiconductor memory elements having such a degree of integration in memory circuits as to produce soft errors by incident .alpha.-rays derived from a packaging material and a package which packages the memory elements and is made from the packaging material, when an .alpha.-rays shielding layer made from a resinous material, which may contain one or more high-purity fillers, containing a total amount of 1 part per billion or less of uranium and thorium is interposed between the memory elements and the package, the generation of soft errors is reduced remarkably.

Abstract: An apparatus for pre-heating resin tablets comprising a resin tablet heater, a switch for setting a reference softening degree and a softening degree detector for the resin tablet. The detector includes a pressure source and a pressure transmitting member coupled to the pressure source and adapted for contact with the resin tablet. The pressure transmitting member is movable a distance representative of the softening degree of the resin tablet being heated due to deformation of the resin tablet.

Abstract: Method of making a semiconductor device which includes applying a solution of a heterocyclic ring-containing polymer in an organic solvent to a desired surface of a semiconductor body and removing the organic solvent from the solution by heat thereby to form a coating of a polymer on the surface, wherein the polymer is a reaction product of a diamine represented by the formula: ##STR1## with a tetracarboxylic acid or anhydride of it. Since the coating exhibits good thermal stability and good electrical properties when applied to the surface of the semiconductor, it is useful as a passivating film.

Abstract: In a semiconductor device, the surface of a semiconductor element is covered with a silicone varnish in which the side chain radical ratio between methyl radicals and phenyl radicals is 20:1 or greater, whereby the element is effectively shielded from the external moisture.

Abstract: In sealing at least a semiconductor element portion of a semiconductor device by the use of a resin, the semiconductor element is covered with a stabilizer or with a resin containing the stabilizer. The stabilizer is adapted to check the migration of a mobile substance such as hydrochloric acid and a mobile ion such as chlorine ion existent within the resin. Owing to the fixation of the ion, the electrical characteristics of the semiconductor device are prevented from being degraded, and constituent parts in the semiconductor device are prevented from being corroded.