Abstract: A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.

Abstract: A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.

Abstract: The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a defective sector), the compulsory signal FMATCH is brought to a HIGH level. The match signal MATCH is forcedly brought to a HIGH level (S22) in compliance with the compulsory signal FMATCH which is at a HIGH level (S21:T). And, verification (S2a) is skipped for the defective sectors, whereby the address signal for identifying the ordinary memory blocks may be utilized for identification of redundant memory blocks.

Abstract: When adjusting reference cells (11), the first reference unit (15) and the second reference unit (17) are used for verification operations of the reference cells (11). The first reference unit (15) provides a lower limit current of an allowable current range for currents provided from a nonvolatile transistor of the reference cells (11), and the second reference unit (17) provides an upper limit current therefor. An amplification signal REFO of the reference cells (11), which is outputted from a sense amplifier (19), is compared with amplification signals LO and HO responsive to the lower and upper limit currents outputted from sense amplifiers (21) and (23), respectively, and a verify operation is carried out to see whether or not the current provided from the nonvolatile transistor is between the lower limit current and the upper limit current of the allowable current range.

Abstract: The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a defective sector), the compulsory signal FMATCH is brought to a HIGH level. The match signal MATCH is forcedly brought to a HIGH level (S22) in compliance with the compulsory signal FMATCH which is at a HIGH level (S21:T). And, verification (S2a) is skipped for the defective sectors, whereby the address signal for identifying the ordinary memory blocks may be utilized for identification of redundant memory blocks.

Abstract: When adjusting the reference cells (11), the first reference unit (15) and the second reference unit (17) are used for a verify operation of the reference cells (11). The first reference unit (15) provides the lower limit current of the allowable current range, which is caused to flow by a nonvolatile transistor of the reference cells (11), and the second reference unit (17) provides the upper limit current thereof. An amplification signal REFO of the reference cells (11), which is outputted from a sense amplifier (19) is compared with amplification signals LO and HO responsive to the lower and upper limit currents outputted from sense amplifiers (21) and (23), and a verify operation is carried out to see whether or not the current caused to flow by the nonvolatile transistor is between the lower limit current and the upper limit current of the allowable current range.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory cells, a plurality of bit lines provided in correspondence to respective columns of the memory cells, a row addressing part connected to each of the plurality of word lines, a column addressing part connected to each pair of the adjacent bit lines, a read/write controller supplied with a cell information to be written into an addressed memory cell and further with a read/write control signal indicating whether the random access memory is to be operated in a reading mode or in a writing mode and acting as a current source in the reading and writing modes, a first current control part provided in each column of the memory cells so as to be connected to one of the bit lines in a column selected by the column addressing part at the first side of each of the memory cells, a second current control part provided in each column