Patents by Inventor Yoshie Inada

Yoshie Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10089151
    Abstract: A method for determining parallel-processing parameters including: randomly generating first sample points each having a coordinate value representing the number of nodes to be used for running a first program and the number of processes per node to be executed in the running of the first program, calculating evaluation values of the respective first sample points based on information collected in the running, calculating a first statistics from the evaluation values; repeating the generating of the first sample points until the first statistic becomes equal to or smaller than a first threshold; and determining, based on a result of interpolation of the evaluation values of the first and the second sample points, the number of nodes and the number of processes that are recommended for running the first program.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 2, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Publication number: 20180210762
    Abstract: A method for determining parallel-processing parameters including: randomly generating first sample points each having a coordinate value representing the number of nodes to be used for running a first program and the number of processes per node to be executed in the running of the first program, calculating evaluation values of the respective first sample points based on information collected in the running, calculating a first statistics from the evaluation values; repeating the generating of the first sample points until the first statistic becomes equal to or smaller than a first threshold; and determining, based on a result of interpolation of the evaluation values of the first and the second sample points, the number of nodes and the number of processes that are recommended for running the first program.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 26, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Patent number: 9459852
    Abstract: While a first code, in an object code generated from a source code, for a loop included in the source code or a second code in the object code is executed, a feature amount concerning the number of times that a condition of a conditional branch is true is obtained. The loop includes the conditional branch, and the conditional branch is coded in the first code. The second code is a code to perform computation of a branch destination for a case where the condition of the conditional branch is true, only for loop indices that were extracted as the aforementioned case. Then, a processor executes, based on the feature amount, the second code or a third code included in the object code. The third code is a code to write, by using a predicated instruction and into a memory, any computation result of computations of branch destinations.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: October 4, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Publication number: 20150234641
    Abstract: While a first code, in an object code generated from a source code, for a loop included in the source code or a second code in the object code is executed, a feature amount concerning the number of times that a condition of a conditional branch is true is obtained. The loop includes the conditional branch, and the conditional branch is coded in the first code. The second code is a code to perform computation of a branch destination for a case where the condition of the conditional branch is true, only for loop indices that were extracted as the aforementioned case. Then, a processor executes, based on the feature amount, the second code or a third code included in the object code. The third code is a code to write, by using a predicated instruction and into a memory, any computation result of computations of branch destinations.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 20, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Patent number: 8549261
    Abstract: Computational unit area selecting units, each of which is provided in individual multiple cores, sequentially select uncomputed computational unit areas in a computational area. Computing units, each of which is provided in the individual multiple cores, perform computation for the selected computational unit areas. In addition, the computing units write computational results in a memory device which is accessible from each of the multiple cores. Computational result transmitting unit of the core performs computational result acquisition and transmission processing in a different time period with respect to each of multiple computational result transmission areas. The computational result acquisition processing is for acquiring, from the memory device, computational results related to the computational result transmission areas.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshie Inada
  • Patent number: 8457935
    Abstract: A data processing method for sampling data from data each varying over time, each of the data being associated with each of grid points arranged in an area, the method includes: dividing the area into blocks; calculating a variation rate of each of the data associated with each of the grid points included in each of the blocks; dividing the blocks into sub-blocks in accordance with the variation rate of the blocks; calculating a variation rate of each set of the data associated with each of the grid points included in each of the sub-blocks; and determining a frequency of sampling data associated with each of the grid points for the sub-blocks of the blocks and for the rest of the blocks in accordance with the variation rate of the sub-blocks and the rest of the blocks.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshie Inada
  • Patent number: 8423330
    Abstract: The data acquisition unit acquires data in correspondence with each dimensional axis and the time axis. The mode setting unit makes setting and clearing of a dimensionality investigation mode. In the dimensionality investigation mode, the axis-determinative variation-rate calculation unit calculates axial data variation rates. The axis determination unit determines whether or not the axial data variation rate corresponding to each axis is low. The objective-axis setting unit sets each axis as an objective axis when the axial data variation rate corresponding to the axis is determined to be high. While the dimensionality investigation mode is cleared, the recording-determinative variation-rate calculation unit calculates axial data variation rates. The recording determination unit determines, on the basis of the axial data variation rate, whether to record the acquired data. The recording unit does not record the data when the data is determined not to be recorded.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshie Inada
  • Publication number: 20120216017
    Abstract: Computational unit area selecting units, each of which is provided in individual multiple cores, sequentially select uncomputed computational unit areas in a computational area. Computing units, each of which is provided in the individual multiple cores, perform computation for the selected computational unit areas. In addition, the computing units write computational results in a memory device which is accessible from each of the multiple cores. Computational result transmitting unit of the core performs computational result acquisition and transmission processing in a different time period with respect to each of multiple computational result transmission areas. The computational result acquisition processing is for acquiring, from the memory device, computational results related to the computational result transmission areas.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Yoshie INADA
  • Publication number: 20100161624
    Abstract: The data acquisition unit acquires data in correspondence with each dimensional axis and the time axis. The mode setting unit makes setting and clearing of a dimensionality investigation mode. In the dimensionality investigation mode, the axis-determinative variation-rate calculation unit calculates axial data variation rates. The axis determination unit determines whether or not the axial data variation rate corresponding to each axis is low. The objective-axis setting unit sets each axis as an objective axis when the axial data variation rate corresponding to the axis is determined to be high. While the dimensionality investigation mode is cleared, the recording-determinative variation-rate calculation unit calculates axial data variation rates. The recording determination unit determines, on the basis of the axial data variation rate, whether to record the acquired data. The recording unit does not record the data when the data is determined not to be recorded.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Publication number: 20100138637
    Abstract: A data processing method for sampling data from data each varying over time, each of the data being associated with each of grid points arranged in an area, the method includes: dividing the area into blocks; calculating a variation rate of each of the data associated with each of the grid points included in each of the blocks; dividing the blocks into sub-blocks in accordance with the variation rate of the blocks; calculating a variation rate of each set of the data associated with each of the grid points included in each of the sub-blocks; and determining a frequency of sampling data associated with each of the grid points for the sub-blocks of the blocks and for the rest of the blocks in accordance with the variation rate of the sub-blocks and the rest of the blocks.
    Type: Application
    Filed: November 2, 2009
    Publication date: June 3, 2010
    Applicant: Fujitsu Limited
    Inventor: Yoshie INADA
  • Publication number: 20090319240
    Abstract: A simulation apparatus performs a plurality of simulations, each at a different time step interval, in parallel. The simulation apparatus calculates results of the simulations based on a plurality of execute objects operating at different time steps specified by a user. The simulation apparatus stores the results of the processed simulations in a shared table, and outputs the results to a visualizing apparatus. The simulation apparatus determines whether the shared table stores simulation data more accurate than processed simulation data. If the processed simulation data is more accurate, the simulation apparatus writes the simulation data to the shared table, and outputs the simulation data to the visualizing apparatus.
    Type: Application
    Filed: August 31, 2009
    Publication date: December 24, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Yoshie Inada
  • Patent number: 4441006
    Abstract: The gap between upper and lower electrodes 1, 2 is measured at constant intervals of time while a contact 5 and a base 6 are pressed by the upper and lower electrodes under a constant pressure. Supply of an electric current to the upper and lower electrodes is controlled upon elapse of a predetermined interval of time after the gap has reached a maximum 18. The amount of metal melted out of a joining interface between the contact 5 and the base 6 is thus quantized to improve and stabilize the quality of joining between the contact 5 and the base 6.
    Type: Grant
    Filed: July 19, 1982
    Date of Patent: April 3, 1984
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazumichi Machida, Yoshie Inada