Abstract: A data processing apparatus for an address boundary check circuit employed in combination with a virtual storage comprises a segment table register provided in association with an address translation table for storing an area discriminating signal indicating whether data to be checked in respect to the address boundary is assigned to unit areas resulting from division of the virtual storage and holding a limit address signal indicating the extent of the area assigned to data which requires an address boundary check of a virtual address accessing the data when the data is found in that area, a register holding a virtual base address for storing a register discriminating signal indicating whether or not the base address is for data to be checked in respect to the address boundary, and an address boundary check circuitry for deciding on the basis of the aforementioned first to third signals whether or not a virtual address calculated in response to an instruction erroneously goes beyond the address boundary.