Abstract: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from generating a first error signal giving notice of detection of a specific error directly to a higher-layer device. A second error signal is output from the physical-layer integrated circuit to the control integrated circuit, giving notice of a high-speed error associated with communication processing and that is detected by the physical-layer integrated circuit. The high-speed error is specified in response to the outputting of the second error signal. A bit is set in the control-side register unit in response to the specifying of a high speed error and the control integrated circuit delivers to the higher-layer device the second error signal.

Abstract: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from generating a first error signal giving notice of detection of a specific error directly to a higher-layer device. A second error signal is output from the physical-layer integrated circuit to the control integrated circuit, giving notice of a high-speed error associated with communication processing and that is detected by the physical-layer integrated circuit. The high-speed error is specified in response to the outputting of the second error signal. A bit is set in the control-side register unit in response to the specifying of a high speed error and the control integrated circuit delivers to the higher-layer device the second error signal.

Abstract: A transceiver module is provided with a transceiver IC (PHY IC) having an XENPAK register group including an status register, and a DCU having an XENPAK register group which emulates the XENPAK register group. The PHY IC has an operation mode in which it does not reply to access to the XENPAK register group by a host while the DCU emulates the structure and function of the XENPAK register group.

Abstract: A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC generates an Unmask signal specifying an error which occurs irrespective of the cause of the error, and outputs it to the DCU. The DCU writes the contents of the status register into a DCU status register as well as the host of the error based on the Unmask signal.

Abstract: A transceiver module is provided with a transceiver IC (PHY IC) having an XENPAK register group including an status register, and a DCU having an XENPAK register group which emulates the XENPAK register group. The PHY IC has an operation mode in which it does not reply to access to the XENPAK register group by a host while the DCU emulates the structure and function of the XENPAK register group.

Abstract: An optical communication module includes a physical-layer unit having a first control unit for receiving a write destination address and NVR data from a host via a serial bus, and for carrying out serial/parallel conversion of the received write destination address and NVR data, and storing them in registers of the first control unit, respectively, and a second control unit for copying the stored write destination address and NVR data to corresponding registers of the second control unit, respectively, and for carrying out parallel/serial conversion of the write destination address and NVR data which are copied to the registers of the second control unit, respectively, and sending them to either an EEPROM or a flash memory of a microcomputer, as well as a write command, via another serial bus to write the NVR data into either the EEPROM or the flash memory of the microcomputer.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.

Abstract: A graphic accelerator includes an image-forming data decode unit, an image memory control unit and a screen data generation unit. The image memory control unit performs a control for writing an output of the image-forming data decode unit to a frame buffer and reading out information stored in the frame buffer. Screen data generation unit restores (interpolates) the color information based on the data read out from the frame buffer and generates screen data. In the frame buffer the information for each pixel is stored in a deleted form including two types of color information among three types of color information consisting of R, G and B. At the reading, the deleted color information is interpolated with the color information of other pixel.

Abstract: When a serial external interface receives a port address from a host device, a CPU reads data at all device addresses corresponding to the port address from a secondary storage medium and writes the data to a primary storage medium. When receiving a device address from host device, serial external interface transmits the data stored in primary storage medium and corresponding to the device address to host device. Therefore, it is possible to transmit the data to host device in short time after receiving the lowest address.

Abstract: An object is to obtain a three-dimensional graphics system capable of color display with reduced operation time. A color data transform portion (2A) extracts the upper k (k<n) bits from n bits for each of R, G and B in RGB original color data (C1) in geometrically-processed three-dimensional data (D1) and transforms the RGB original color data (C1) into reduced color data (C2) in such a manner that the sets of k bits are assigned respectively to R, G and B, thus providing color data for three-dimensional data (D2) to be used in the drawing operation. A drawing operation portion (3A) applies drawing operations including color processing operation based on the reduced color data (C2) to the three-dimensional data for drawing operation (D2) obtained from the color data transform portion (2A) and outputs three-dimensional graphic drawing data to a drawing unit (4). The drawing unit (4) displays three-dimensional graphics in color on a display screen in a display unit.

Abstract: A bus (3) includes a data bus (3a) and a clock bus (3b). The data bus (3a) is used for propagation of data MDIO conforming to the MDIO interface standards performed between a host controller IC (40) and a transceiver IC (1), and for propagation of data (SDA) conforming to the I2C standards performed between the transceiver IC (1) and a peripheral IC (2). Meanwhile, the clock bus (3b) is used for propagation of clock (MDC) conforming to the MDIO interface standards performed between the host controller IC (40) and the transceiver IC (1), and for propagation of clock (SCL) conforming to the I2C standards performed between the transceiver IC (1) and the peripheral IC (2).

Abstract: A three-dimensional graphic processing device includes an identifying portion for identifying whether the vertex data of a polygon to be drawn is an absolute value or a relative value, an operation unit for operating to obtain the absolute value of vertex data identified as a relative value by the identifying portion and a set up circuit for generating data necessary for drawing based on the absolute value of the vertex data obtained by the operation unit. The operation unit operates to obtain the absolute value of vertex data identified as a relative value by the identifying portion, and therefore the vertex data of a polygon can be expressed by a relative value. As a result, the data amount of polygon data can be reduced, which permits the drawing throughput to be improved.

Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.

Abstract: A disparity signal and a 6-bit subblock are provided to a 5B/6B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 5B/6B decoding part. The disparity signal and a 4-bit subblock are provided to a 3B/4B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 3B/4B decoding part. A data hold circuit delays the disparity signal by one clock and then provides the resulting signal to the 5B/6B decoding part. At least part of the decoding processing in the 3B/4B decoding part is executed in parallel with the obtaining of the disparity signal in the 5B/6B decoding part.

Abstract: An optical communication module (10) comprises a transmitting laser (5), a receiving element (6), and a peripheral IC (2) for controlling the transmitting laser (5) and the receiving element (6). The peripheral IC (2) is connected to a transceiver IC (1) through a serial bus (4) for peripheral IC. The transceiver IC (1) of the optical communication module (10) is connected to a high-order layer circuit (21) through a serial bus (3) for high-order layer. The transceiver IC (1) comprises a register 15 for high-order layer including an NV register and a DOM register, and an additional register (16) including an LASI register and a VS register. Both the serial bus (3) for high-order layer and the serial bus (4) for peripheral IC are connected to the register (15) for high-order layer and the additional register (16).

Abstract: A graphic accelerator includes a RGB/YUV conversion unit converting color information of the RGB format included in the drawing instruction into a format including luminance and color difference components, a drawing instruction execution unit compressing the color difference component converted by the RGB/YUV conversion unit and generates pixel information according to the drawing instruction, a screen data output unit expanding pixel information generated by the drawing instruction execution unit, and a YUV/RGB conversion unit converting the pixel information expanded by the screen data output unit into pixel information of the RGB format. Therefore, the amount of data of the color difference component can be reduced to improve the processing speed.

Abstract: An MDIO interface transmits and receives data to and from a host device through an upper serial bus. An MDIO interface transmits and receives data to and from a client device through a lower serial bus. A CPU controls the MDIO interface and the MDIO interface, and controls data transfer between the host device and the client device. It is, therefore, possible that the CPU controls the client device connected to the lower serial bus.

Abstract: A microcomputer system includes a transceiver used in Ethernet (R) and a microcomputer backing up data in the transceiver. The transceiver, upon receiving a request for data write in a primary storage medium from a host device, outputs an interruption request to the microcomputer. The microcomputer, upon receiving the interruption request, reads data written in the primary storage medium and writes the data in a second storage medium. Therefore, if the data written in the primary storage medium is lost due to a momentary power failure and the like, the data of the primary storage medium can be restored.

Abstract: When a serial external interface receives a port address from a host device, a CPU reads data at all device addresses corresponding to the port address from a secondary storage medium and writes the data to a primary storage medium. When receiving a device address from host device, serial external interface transmits the data stored in primary storage medium and corresponding to the device address to host device. Therefore, it is possible to transmit the data to host device in short time after receiving the lowest address.

Abstract: Obtained is a method of generating data for three-dimensional graphics which can perform three-dimensional graphics display at a practical level also in the case in which a three-dimensional graphics system having a comparatively low throughput is used. Object data (10) and scene data (11) are sequentially read in one frame unit (S1), and an operation processing including a geometric operation and a light source computation is executed for the data read at the step (S1) (S2 to S6). Furthermore, an optimization processing is executed such that a data amount of data for 3D-CG can be reduced based on a hardware constraint including a constraint related to a throughput of a three-dimensional graphics system (S7, S8). Thus, the data for 3D-CG are obtained.