Patents by Inventor Yoshifumi Kanetaka

Yoshifumi Kanetaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8525333
    Abstract: An electronic device includes the electronic element, the interposer substrate, on one surface of which the electronic element is mounted, and the interconnection substrate, on one surface of which the interposer substrate is mounted. One portion of the connection parts is an electrical connection part that electrically interconnects the interposer substrate and the interconnection substrate. The remaining portion is a dummy connection part that produces no functional deficiency even when the dummy connection part does not electrically interconnect the interposer substrate with the interconnection substrate. The dummy connection part includes at least one of the connection parts that at least partially overlap with the electronic element in a plan projection and are preferably arranged along an outer rim of the plan projection of the electronic element.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshifumi Kanetaka
  • Publication number: 20110006433
    Abstract: An electronic device includes the electronic element, the interposer substrate, on one surface of which the electronic element is mounted, and the interconnection substrate, on one surface of which the interposer substrate is mounted. One portion of the connection parts is an electrical connection part that electrically interconnects the interposer substrate and the interconnection substrate. The remaining portion is a dummy connection part that produces no functional deficiency even when the dummy connection part does not electrically interconnect the interposer substrate with the interconnection substrate. The dummy connection part includes at least one of the connection parts that at least partially overlap with the electronic element in a plan projection and are preferably arranged along an outer rim of the plan projection of the electronic element.
    Type: Application
    Filed: March 17, 2009
    Publication date: January 13, 2011
    Inventor: Yoshifumi Kanetaka
  • Patent number: 7820917
    Abstract: A circuit board includes a plurality of through holes into which a plurality of leads of one electronic devices are inserted and soldered with lead free solder. Among these through holes, the volume of through hole into which the outermost end lead of leads of the electronic device is inserted, is set greater than the volume of through hole, into which the lead at the position nearest to the center of the electronic device is inserted.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: October 26, 2010
    Assignee: NEC Corporation
    Inventors: Yoshifumi Kanetaka, Naomi Ishizuka
  • Publication number: 20080190657
    Abstract: A circuit board includes a plurality of through holes (14, 44) into which a plurality of leads (18) of one electronic devices are inserted and soldered. Among these through holes (14, 44), the volume of through hole (14b, 24b, 34b, 44b, 54, 64b) into which the outermost end lead of leads (18) of the electronic device is inserted, is set greater than the volume of through hole (14a, 44a), into which the lead at the position nearest to the center of the electronic device is inserted.
    Type: Application
    Filed: January 6, 2005
    Publication date: August 14, 2008
    Inventors: Yoshifumi Kanetaka, Naomi Ishizuka