Patents by Inventor Yoshifumi MATSUSAKI

Yoshifumi MATSUSAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020821
    Abstract: A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (11-1) of this disclosure, included in a transmission device (1) of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator (23) of this disclosure, included in a reception device (2) of this disclosure, decodes digital data encoded by the encoder (11-1).
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 10, 2018
    Assignee: NIPPON HOSO KYOKAI
    Inventors: Youichi Suzuki, Akinori Hashimoto, Shoji Tanaka, Kenichi Tsuchida, Takeshi Kimura, Yoshifumi Matsusaki
  • Publication number: 20170302296
    Abstract: A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (11-1) of this disclosure, included in a transmission device (1) of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator (23) of this disclosure, included in a reception device (2) of this disclosure, decodes digital data encoded by the encoder (11-1).
    Type: Application
    Filed: November 13, 2014
    Publication date: October 19, 2017
    Applicant: NIPPON HOSO KYOKAI
    Inventors: Youichi SUZUKI, Akinori HASHIMOTO, Shoji TANAKA, Kenichi TSUCHIDA, Takeshi KIMURA, Yoshifumi MATSUSAKI
  • Publication number: 20170163376
    Abstract: A modulator, demodulator, transmission device, and reception device for digital data that have excellent resistance to noise are provided. A modulator according to one aspect of this disclosure includes a modulation mapper (15) that performs 16APSK mapping at a radius ratio of 2.87 when the LDPC code rate is 93/120. A modulator according to another aspect of this disclosure includes a modulation mapper (15) that performs 32APSK mapping at a second inner circle to first inner circle radius ratio of 2.87 and an outer circle to first inner circle radius ratio of 5.33 when the LDPC code rate is 93/120. The modulator is included in a transmission device (1) according to this disclosure. A demodulator according to this disclosure includes a quadrature detector (21) that performs demodulation corresponding to the modulator. The demodulator is included in a reception device (2) according to this disclosure.
    Type: Application
    Filed: November 13, 2014
    Publication date: June 8, 2017
    Applicant: NIPPON HOSO KYOKAI
    Inventors: Youichi SUZUKI, Akinori HASHIMOTO, Shoji TANAKA, Kenichi TSUCHIDA, Takeshi KIMURA, Yoshifumi MATSUSAKI
  • Publication number: 20160294417
    Abstract: A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (11-1) of this disclosure, included in a transmission device (1) of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator (23) of this disclosure, included in a reception device (2) of this disclosure, decodes digital data encoded by the encoder (11-1).
    Type: Application
    Filed: November 13, 2014
    Publication date: October 6, 2016
    Applicant: NIPPON HOSO KYOKAI
    Inventors: Youichi SUZUKI, Akinori HASHIMOTO, Shoji TANAKA, Kenichi TSUCHIDA, Takeshi KIMURA, Yoshifumi MATSUSAKI
  • Publication number: 20160294507
    Abstract: A modulator, demodulator, transmission device, and reception device for digital data that have excellent resistance to noise are provided. A modulator according to one aspect of this disclosure includes a modulation mapper (15) that performs 16APSK mapping at a radius ratio of 2.87 when the LDPC code rate is 93/120. A modulator according to another aspect of this disclosure includes a modulation mapper (15) that performs 32APSK mapping at a second inner circle to first inner circle radius ratio of 2.87 and an outer circle to first inner circle radius ratio of 5.33 when the LDPC code rate is 93/120. The modulator is included in a transmission device (1) according to this disclosure. A demodulator according to this disclosure includes a quadrature detector (21) that performs demodulation corresponding to the modulator. The demodulator is included in a reception device (2) according to this disclosure.
    Type: Application
    Filed: November 13, 2014
    Publication date: October 6, 2016
    Applicant: NIPPON HOSO KYOKAI
    Inventors: Youichi SUZUKI, Akinori HASHIMOTO, Shoji TANAKA, Kenichi TSUCHIDA, Takeshi KIMURA, Yoshifumi MATSUSAKI