Patents by Inventor Yoshifumi Moriyama

Yoshifumi Moriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281107
    Abstract: In a semiconductor device including a semiconductor device chip mounted on a substrate and a solder bump electrode formed on an electrode film of the substrate, a pillar-form conductive paste is formed on a first surface portion of the electrode film, and a solder bump electrode is formed to cover the pillar-form conductive paste and a second surface portion of the electrode film on which the pillar-form conductive paste is not formed. With this arrangement, it is possible to realize a predetermined bump height, and also to prevent a bump from collapsing at the time of mounting.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: August 28, 2001
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 6195260
    Abstract: A flexible printed circuit unit includes a flexible printed circuit board having one or more electronic parts mounted on a front surface thereof. A reverse side reinforcing plate is provided at a location of the reverse side of the flexible printed circuit board corresponding to a region in which the electronic parts are mounted. An upper reinforcing structure is provided on the front surface of the flexible printed circuit board for covering at least one of the electronic parts.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: February 27, 2001
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 6143991
    Abstract: A connection electrode structure includes a wiring conductor layer formed on a printed wiring board, a bump electrode portion formed on an outer end portion of the wiring conductor layer and formed by an electroplating of Cu, a pad electrode portion formed inwardly adjacent to the bump electrode portion and continuous with it, a Ni/Au layer covering the bump electrode portion and the pad electrode portion, and a solder resist layer formed on a portion of the wiring conductor layer at an inside of the pad electrode portion to stop solder flow.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: November 7, 2000
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 6028357
    Abstract: In a semiconductor device including a semiconductor device chip mounted on a substrate and a solder bump electrode formed on an electrode film of the substrate, a pillar-form conductive paste is formed on a first surface portion of the electrode film, and a solder bump electrode is formed to cover the pillar-form conductive paste and a second surface portion of the electrode film on which the pillar-form conductive paste is not formed. With this arrangement, it is possible to realize a predetermined bump height, and also to prevent a bump from collapsing at the time of mounting.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 5962917
    Abstract: A semiconductor device package comprises a circuit substrate, a semiconductor device chip mounted on the circuit substrate, a plurality of end-face halved through-holes formed on an end-face of the circuit substrate, in the form obtained by halving a through hole along its center axis, and having an inner side surface coated with a conductor film, a plurality of wiring conductors formed on an upper surface of the circuit substrate and connected to the end-face halved through-holes, a plurality of external electrode conductors formed on a lower surface of the circuit substrate and connected to the end-face halved through-holes, and a solder resist provided to partially cover the external electrode conductors for separating an end of the external electrode conductors from the end-face halved through-holes.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 5, 1999
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 5388029
    Abstract: In a semiconductor chip carrier which has a rectangular insulating substrate having four corners and electrode leads deposited on a peripheral surface of the substrate and which is mounted onto a circuit board with each electrode lead being connected to the corresponding board electrode through a solder mass, widths of the electrode leads are wider at each of the four corners than those of the electrode leads located at positions except the four corners. An area of the contact through the solder between each electrode lead positioned at each corner and the corresponding board electrode is wider than that between each of the other electrode lead and each corresponding board electrode. As each electrode lead positioned at each corner is strongly connected to the board electrode, it is seldom peeled off from the board electrode even when the circuit board is twisted or warped during or after the process of mounting the chip carrier onto the circuit board.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: February 7, 1995
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama