Abstract: In a parallel processor system, each processor is connected to a secondary memory. A main memory of a sender processor has first small buffers and a main memory of a receiver processor has second small buffers. The sender processor divides data correspondingly to destinations and transmits the data to receiver processors through the first small buffers. Each receiver processor further divides the received data, stores the divided data in a bucket storage region in the secondary memory, and performs a designated process. Since data is divided in two stages, with a very reduced number of small buffers, bucket tuning process can be performed.

Abstract: A data processing system has a dynamic address translation function for dynamically translating virtual addresses into real addresses and processes data. The system employs a plurality of control registers for managing the developed addresses of address translation tables and a selector for selecting one of the control registers. The control register selected by the selector specifies one of the address translation tables, which is used to dynamically translate a virtual address into a real address.

Abstract: A parallel processor apparatus, which enables a blocking work for assuring a bucket write/read performance with a storage quantity in an ordinary range so as to largely improve the bucket write/read performance, has a first dividing unit for dividing data that is an object of a process into plural sets of bucket groups each of which is a set of tuples of plural sorts when the data is transmitted from a first processor group to an intermediate processor group to temporarily store the data in the intermediate processor group. The parallel processor apparatus further includes a second dividing unit for reading each of the plural sets of bucket groups to divide it into buckets each of which is a set of tuples of the same sort when the data is transmitted from the intermediate processor group to a second processor group, and storing the data in the second processor group.

Abstract: The present invention relates to a parallel processor system that can reduce the hardware circuit amount of the portions except a memory capacity. In the parallel processor system, each S-DPr (Source Data Processor) executes a local leveling process to level equally all loads to T-DPrs (Target Data Processor) related to data sent from itself so that the leveling is performed to all the T-DPrs and the chunks as a whole. The parallel processor system is applicable to super-database computers that perform the MIMD-type process.

Abstract: A virtual computer system including a plurality of virtual machines running in a central processing unit with time shared, an input/output unit generating an input/output interrupt request, and a specific instruction generating part for generating a specific instruction indicating a priority to one of the virtual machines which is running. The system further includes a decision part for determining whether the input/output interrupt request addressed to one of the virtual machines has a priority equal to that indicated by the specific instruction and for generating an interrupt accepting signal when the decision result is affirmative. Moreover, the system includes a monitor part for transferring a right to use the central processing unit from the one of the virtual machines which is running to the one of the virtual machines which is addressed by the input/output interrupt request when the interrupt accepting signal from the decision part is supplied to the monitor part.

Abstract: A virtual computer system has a plurality of virtual computers and a virtual computer monitor for monitoring the virtual computers and for providing translation information describing the relationship between a virtual identification of the input/output apparatus structure to be recognized by the virtual computers and a physical identification to be actually used by the input/output apparatus structure. A hardware dynamically creates a subchannel necessary for performing an input/output process of the virtual computers and translation information when the virtual computer monitor provides the translation information to the hardware. The hardware translates the virtual identification to the physical identification based on the translation information when the virtual computer issues the input/output instruction, and for identifying the subchannel, thereby performing the input/output process.