Patents by Inventor Yoshifumi Ohnishi
Yoshifumi Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230324536Abstract: A radar signal processing device includes: a shielding length calculating unit (61) which calculates, based on a reception signal received by an antenna that transmits and receives radio waves, a shielding length (L2), which is the horizontal length of a region where a transmission signal transmitted from the antenna is shielded by a shielding object (13) above a reference plane; and a vertical height calculating unit (62) which calculates, based on the shielding length and the positional relationship between the shielding object and the antenna, the height (H2) of the shielding object from the reference plane.Type: ApplicationFiled: June 1, 2023Publication date: October 12, 2023Applicant: FURUNO ELECTRIC CO., LTD.Inventors: Tetsuya MIYAGAWA, Yoshifumi OHNISHI
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Patent number: 9964639Abstract: A radar apparatus configured to prevent a harmonic generated by a limiter from being transmitted outside is provided. The radar apparatus includes a harmonic processor between a circulator and a limiter. The harmonic processor includes harmonic processing stubs, and a compensation stub. The harmonic processing stubs attenuate the harmonic which is generated when the limiter attenuates a transmission signal passed through the circulator. The compensation stub cancels a change of a susceptance caused by disposing the harmonic processing stubs.Type: GrantFiled: November 5, 2013Date of Patent: May 8, 2018Assignee: Furuno Electric Co., Ltd.Inventors: Takuya Okimoto, Yoshifumi Ohnishi
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Patent number: 9684062Abstract: A radar antenna device is provided for rotating an antenna unit which successively emits transmission signals. It is configured to reduce the capacity of an electric power source for supplying electric power to a transmission circuit, a drive unit and the like. A radar antenna device is comprised with an antenna unit and a control unit. The antenna unit is driven by a drive unit to rotate and emits successively transmission signals generated by a transmission circuit into an outer space. After electric power is supplied to the drive unit to be driven, the control unit controls the transmission circuit in response to the transmission start signal from the transmission start signal producer so that the electric power for the transmission will be supplied to the transmission circuit.Type: GrantFiled: October 14, 2014Date of Patent: June 20, 2017Assignee: FURUNO ELECTRIC COMPANY LIMITEDInventors: Yoshifumi Ohnishi, Suminori Ekuni, Motoji Kondo
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Patent number: 9551782Abstract: A radar apparatus is provided. The radar apparatus includes a transmitter configured to transmit radar signals via a radar antenna, a receiver configured to receive reflection waves that are echoes of the radar signals, via the radar antenna, a radar image generating module configured to generate a radar image based on the reflection waves received by the receiver, a performance monitor configured to measure performance of at least one of the transmitter and the receiver, and a controller configured to cause the performance monitor to perform the measurement while the transmission of the radar signals is suspended.Type: GrantFiled: May 27, 2014Date of Patent: January 24, 2017Assignee: FURUNO ELECTRIC COMPANY LIMITEDInventors: Katsuyuki Yanagi, Yoshifumi Ohnishi
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Radar performance monitor, pulse-compression radar apparatus, and radar performance measuring method
Patent number: 9310469Abstract: A radar performance monitor is provided. The monitor includes a receiver for receiving a transmission signal of which a temporal change of a frequency is non-linear, the transmission signal being transmitted from a radar unit of a pulse-compression radar apparatus, and a response signal generator for generating a response signal of which a temporal change of a frequency is linear and transmitting the response signal to the radar unit as a response to the transmission signal received by the receiver.Type: GrantFiled: August 20, 2013Date of Patent: April 12, 2016Assignee: Furuno Electric Co., Ltd.Inventor: Yoshifumi Ohnishi -
Publication number: 20150309170Abstract: A radar apparatus configured to prevent a harmonic generated by a limiter from being transmitted outside is provided. The radar apparatus includes a harmonic processor between a circulator and a limiter. The harmonic processor includes harmonic processing stubs , and a compensation stub. The harmonic processing stubs attenuate the harmonic which is generated when the limiter attenuates a transmission signal passed through the circulator. The compensation stub cancels a change of a susceptance caused by disposing the harmonic processing stubs.Type: ApplicationFiled: November 5, 2013Publication date: October 29, 2015Applicant: FURUNO ELECTRIC CO., LTD.Inventors: Takuya Okimoto, Yoshifumi Ohnishi
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Publication number: 20150102958Abstract: A radar antenna device is provided for rotating an antenna unit which successively emits transmission signals. It is configured to reduce the capacity of an electric power source for supplying electric power to a transmission circuit, a drive unit and the like. A radar antenna device is comprised with an antenna unit and a control unit. The antenna unit is driven by a drive unit to rotate and emits successively transmission signals generated by a transmission circuit into an outer space. After electric power is supplied to the drive unit to be driven, the control unit controls the transmission circuit in response to the transmission start signal from the transmission start signal producer so that the electric power for the transmission will be supplied to the transmission circuit.Type: ApplicationFiled: October 14, 2014Publication date: April 16, 2015Inventors: Yoshifumi OHNISHI, Suminori EKUNI, Motoji KONDO
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Publication number: 20140354468Abstract: A radar apparatus is provided. The radar apparatus includes a transmitter configured to transmit radar signals via a radar antenna, a receiver configured to receive reflection waves that are echoes of the radar signals, via the radar antenna, a radar image generating module configured to generate a radar image based on the reflection waves received by the receiver, a performance monitor configured to measure performance of at least one of the transmitter and the receiver, and a controller configured to cause the performance monitor to perform the measurement while the transmission of the radar signals is suspended.Type: ApplicationFiled: May 27, 2014Publication date: December 4, 2014Applicant: FURUNO Electric Company LimitedInventors: Katsuyuki YANAGI, Yoshifumi OHNISHI
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RADAR PERFORMANCE MONITOR, PULSE-COMPRESSION RADAR APPARATUS, AND RADAR PERFORMANCE MEASURING METHOD
Publication number: 20140300507Abstract: A radar performance monitor is provided. The monitor includes a receiver for receiving a transmission signal of which a temporal change of a frequency is non-linear, the transmission signal being transmitted from a radar unit of a pulse-compression radar apparatus, and a response signal generator for generating a response signal of which a temporal change of a frequency is linear and transmitting the response signal to the radar unit as a response to the transmission signal received by the receiver.Type: ApplicationFiled: August 20, 2013Publication date: October 9, 2014Applicant: Furuno Electric Co., Ltd.Inventor: Yoshifumi Ohnishi -
Patent number: 8742979Abstract: This disclosure provides a range side lobe removal device, which includes a pulse compressor for acquiring a reception signal from a radar antenna and generating a pulse-compressed signal by performing a pulse compression of the reception signal, a pseudorange side lobe generator for generating a pseudo signal of range side lobes of the pulse-compressed signal based on the reception signal, and a signal remover for removing a component corresponding to the pseudo signal from the pulse-compressed signal.Type: GrantFiled: April 11, 2012Date of Patent: June 3, 2014Assignee: Furuno Electric Company LimitedInventor: Yoshifumi Ohnishi
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Publication number: 20120262332Abstract: This disclosure provides a range side lobe removal device, which includes a pulse compressor for acquiring a reception signal from a radar antenna and generating a pulse-compressed signal by performing a pulse compression of the reception signal, a pseudorange side lobe generator for generating a pseudo signal of range side lobes of the pulse-compressed signal based on the reception signal, and a signal remover for removing a component corresponding to the pseudo signal from the pulse-compressed signal.Type: ApplicationFiled: April 11, 2012Publication date: October 18, 2012Inventor: Yoshifumi OHNISHI
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Patent number: 8115674Abstract: This disclosure provides a target object detection device for detecting different areas by different pulse-shaped signals detecting an area from an antenna position to a given distance. The device includes a transmission module for transmitting different pulse-shaped transmission signals at predetermined timings, a reception module for receiving their reflection signals to generate a reception signal, a saturation detection module for comparing a level of each of the reception signals with a predetermined threshold to detect saturation of the reception signal, and an image forming module for forming a detection image based on the reception signals. The transmission module generates an alternative pulse-shaped signal that is different from the transmitted pulse-shaped transmission signal when the saturation detection module detects the saturation of the reception signal.Type: GrantFiled: July 6, 2010Date of Patent: February 14, 2012Assignee: Furuno Electric Company LimitedInventor: Yoshifumi Ohnishi
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Publication number: 20110001661Abstract: This disclosure provides a target object detection device for detecting different detection areas by different pulse-shaped signals and synthesizing detected information to detect an area from an antenna position to a given distance. The device includes a transmission module for transmitting at least two or more different pulse-shaped transmission signals at predetermined timings, a reception module for receiving a reflection signal of each of the transmitted pulse-shaped transmission signals to generate a reception signal, a saturation detection module for comparing a level of each of the reception signals with a predetermined threshold to detect saturation of the reception signal, and an image forming module for forming a detection image based on the reception signals. The transmission module generates an alternative pulse-shaped signal that is different from the transmitted pulse-shaped transmission signal when the saturation detection module detects the saturation of the reception signal.Type: ApplicationFiled: July 6, 2010Publication date: January 6, 2011Inventor: Yoshifumi Ohnishi
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Patent number: 7598806Abstract: There is provided a distortion compensation circuit that can compensate for the nonlinearity of an amplifier having the characteristic that the gain is reduced and the phase is delayed with an increase in input power. An inductor 112 is connected in series with a diode 105 of a distortion compensation circuit 100. The resistance components of the diode 105 decrease with an increase in input power, so that the effect of the impedance of the inductor 112 connected in series with the diode 105 appears, and the impedance of the distortion compensation circuit 100 becomes inductive, producing the characteristic that the phase is advanced. At the same time, the resistance components of the diode 105 decrease with an increase in input power, thus producing the characteristic that the loss is reduced and the gain is increased.Type: GrantFiled: June 28, 2005Date of Patent: October 6, 2009Assignee: Furuno Electric Company LimitedInventors: Takuo Kashiwa, Yoshifumi Ohnishi
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Publication number: 20070262816Abstract: There is provided a distortion compensation circuit that can compensate for the nonlinearity of an amplifier having the characteristic that the gain is reduced and the phase is delayed with an increase in input power. An inductor 112 is connected in series with a diode 105 of a distortion compensation circuit 100. The resistance components of the diode 105 decrease with an increase in input power, so that the effect of the impedance of the inductor 112 connected in series with the diode 105 appears, and the impedance of the distortion compensation circuit 100 becomes inductive, producing the characteristic that the phase is advanced. At the same time, the resistance components of the diode 105 decrease with an increase in input power, thus producing the characteristic that the loss is reduced and the gain is increased.Type: ApplicationFiled: June 28, 2005Publication date: November 15, 2007Applicant: FURUNO ELECTRIC COMPANY LIMITEDInventors: Takuo Kashiwa, Yoshifumi Ohnishi
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Patent number: 6649487Abstract: A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.Type: GrantFiled: January 17, 2002Date of Patent: November 18, 2003Assignee: Hitachi, Ltd.Inventors: Takashi Hashimoto, Yoshifumi Ohnishi, Toshiyuki Kikuchi
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Patent number: 6432799Abstract: A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.Type: GrantFiled: November 24, 1999Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Hashimoto, Yoshifumi Ohnishi, Toshiyuki Kikuchi
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Publication number: 20020102815Abstract: A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.Type: ApplicationFiled: January 17, 2002Publication date: August 1, 2002Inventors: Takashi Hashimoto, Yoshifumi Ohnishi, Toshiyuki Kikuchi
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Patent number: 6027983Abstract: A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.Type: GrantFiled: May 31, 1995Date of Patent: February 22, 2000Assignee: Hitachi, Ltd.Inventors: Takashi Hashimoto, Yoshifumi Ohnishi, Toshiyuki Kikuchi