Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.

Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.

Abstract: A memory card connector includes first and second connectors including first and second housings having first and second storage sections, respectively, and first and second contacts which connect with terminals of first and second memory cards removably-inserted into the first and second storage sections, respectively. The first and second connectors are superposed on each other in a direction of thickness thereof. Each first contact includes a first tail which is mountable to a circuit board and positioned on an outer peripheral side of a first side surface of the first housing. The second housing includes a second side surface located at a different position from the first side surface as viewed in the thickness direction. Each second contact includes a second tail which is mountable to the circuit board and positioned on an outer peripheral side of the second side surface.

Abstract: A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive.

Abstract: A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration.

Abstract: A memory card connector includes first and second connectors including first and second housings having first and second storage sections, respectively, and first and second contacts which connect with terminals of first and second memory cards removably-inserted into the first and second storage sections, respectively. The first and second connectors are superposed on each other in a direction of thickness thereof. Each first contact includes a first tail which is mountable to a circuit board and positioned on an outer peripheral side of a first side surface of the first housing. The second housing includes a second side surface located at a different position from the first side surface as viewed in the thickness direction. Each second contact includes a second tail which is mountable to the circuit board and positioned on an outer peripheral side of the second side surface.

Abstract: A semiconductor light-emitting element mounting module includes a metal conductor plate including at least one connection surface formed on one side thereof, wherein a semiconductor light-emitting element is connectable to the connection surface; a pair of terminals provided away from the connection surface and which are connectable to the connection surface to be electrically conductive therewith; a surface-insulation portion formed from a resin material, wherein the surface-insulation portion covers the entire surface of the metal conductor plate except for the connection surface. The pair of terminals are connectable with a corresponding pair of terminals that are provided on another semiconductor light-emitting element mounting module.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.

Abstract: To provide a screw for injection molding and a plasticizing device which can ensure downsizing of the plasticizing device by decreasing an L/D ratio as well as keeping a molten resin to be discharged while stably molten and discharged. In the screw 1a, 1b, 1c, the L/D ratio obtained by dividing an effective length L by an external diameter D is 10 or less, and a flight pitch is designed so that a thread length falls within a range of 30 to 300% of a screw with a square pitch having the same diameter and the L/D ratio of 20 to 24. A torpedo plate 13 with a through-hole is installed in the vicinity of the top end of the screw, inside the through-hole arranged is a spindle-shaped torpedo 12 supported by one or more supporting pieces, and between an internal surface of the through-hole and an outer surface of the torpedo 12, formed is a path 17 of plasticized resin material.

Abstract: To provide a plasticizing apparatus for resin material allowing downsizing of an injection molding apparatus while stabilizing a plastication state of a resin material without raising a heating temperature for a plasticizing barrel. On the inner surface of a plasticizing barrel 2 for plasticizing the resin material, one or more lines of a heat transfer piece 21 shaped like a ridge is/are disposed in a protrusion condition in a spiral or a straight line, and on the outer surface of the barrel 2, one or more lines of a heat receiving piece 22 is/are disposed in a protrusion condition in a spiral or a straight line, in the pitch of which, a heater 3 is fit, and in the vicinity of an opening 23 for feeding the resin material into the barrel 2, a radiating member 24 which radiates heat inside the barrel 2 into the outside air is disposed in a protrusion condition.

Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.

Abstract: In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.