Abstract: When a particular bank is selected the output from the data AMP of that bank is inputted and latched, and the data corresponding to the output of the data AMP is transmitted to the common data transmission line RWBUS. When the particular bank is not selected, the data on the common data transmission line RWBUS is latched to hold the final data of the previous bank during the cycle time tCK period even when the bank is switched over during the read operation, and the data on the common data transmission line RWBU can be latched, thereby enabling increased speed of the read action.

Abstract: A semiconductor memory device includes a burst counter for receiving an external address signal and generating an internal address signal for a predetermined burst length in synchronization with an external clock, and a switching circuit arranged such that, during the test mode, an address signal to be inputted to a column decoder which receives and decodes said internal address signal is switched, unlike under a normal mode, to be variable at each cycle, and a column select line to be outputted from said column decoder is configured so as to be variable at each cycle.

Abstract: To make a memory system smaller, a memory system includes a plurality of memory cell arrays including a plurality of pairs of bit lines, a plurality of first data amplifiers for amplifying data of corresponding pairs of bit lines, a reference voltage circuit for outputting a reference voltage level, and a plurality of second amplifiers for receiving an output of the corresponding first data amplifier and the reference voltage level, for judging which voltage level is higher between the output of the corresponding first data amplifier and the reference voltage level, and for amplifying the voltage level being higher.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in column and row directions in a matrix manner, and an oscillating section for oscillating in response to a self-refresh operation mode to generate an oscillation signal. A timer signal generating section outputs, as a timer signal based on the oscillation signal from the oscillating section, a first clock signal in a normal operation mode and a second clock signal in a test operation mode, the second clock signal being longer than the first clock signal and associated with a maximum usable temperature of the semiconductor memory device.