Patents by Inventor Yoshifumi Takata
Yoshifumi Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8716122Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.Type: GrantFiled: February 6, 2013Date of Patent: May 6, 2014Assignee: Renesas Electronics CorporationInventors: Takuro Honma, Yoshifumi Takata
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Patent number: 8390134Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.Type: GrantFiled: May 19, 2010Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Takuro Homma, Yoshifumi Takata
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Publication number: 20100295044Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.Type: ApplicationFiled: May 19, 2010Publication date: November 25, 2010Inventors: Takuro HOMMA, Yoshifumi Takata
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Patent number: 6890857Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.Type: GrantFiled: October 28, 2002Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
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Patent number: 6777738Abstract: A semiconductor integrated circuit is formed with a contact hole through first and second interlayer insulating films. The contact hole contains first and second high melting point metals forming a plug forming a recess below an upper surface of the second interlayer insulating film. An interconnection layer is formed in electrical connection with the metal plug. In an embodiment of the present invention, the second insulating film has a thickness greater than the depth of the recess. In another embodiment of the present invention, the contact hole increases in diameter toward the upper surface of the second insulating film thereby enhancing filling of the contact hole with the first and second metals.Type: GrantFiled: November 17, 1999Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventor: Yoshifumi Takata
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Patent number: 6727170Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.Type: GrantFiled: July 13, 2001Date of Patent: April 27, 2004Assignee: Renesas Technology Corp.Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
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Publication number: 20030109100Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.Type: ApplicationFiled: November 26, 2002Publication date: June 12, 2003Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, RYODEN SEMICONDUCTOR SYSTEM ENGINEERING CORPORATIONInventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
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Publication number: 20030052339Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.Type: ApplicationFiled: October 28, 2002Publication date: March 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
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Patent number: 6500675Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.Type: GrantFiled: April 19, 2001Date of Patent: December 31, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
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Patent number: 6476491Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer. formed from one selected from precious metals and alloys containing the precious metals as main components.Type: GrantFiled: January 10, 2001Date of Patent: November 5, 2002Assignee: Mitsubishi Denki Kabushiki KaihsaInventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
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Publication number: 20020140017Abstract: A fifth interlayer insulating film is formed on a fourth interlayer insulating film. A third contact hole is formed in such a manner as to pass through the fourth and fifth interlayer insulating films. First and second high melting point metal films are deposited on the inner surface of the third contact hole and the surface of the fifth interlayer insulating film, and then etched-back until the fifth interlayer insulating film is exposed, to form a metal plug. A second interconnection layer is formed on the fifth interlayer insulating film in such a manner as to be conducted to the metal plug. The thickness of the fifth interlayer insulating film is set to be larger than the depth of a recess formed by depressing the upper end surface of the metal plug upon etching-back.Type: ApplicationFiled: November 17, 1999Publication date: October 3, 2002Inventor: YOSHIFUMI TAKATA
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Patent number: 6448658Abstract: A fourth and a fifth interlayer insulating film are formed and a connecting hole which passes through these films is formed. The connecting hole is filled with a metallic plug. The exposed surface of the fifth interlayer insulating film and metallic plug is etched back by dry etching in an atmosphere containing CF4 gas. Thus, the step difference between the surfaces of the metallic plug and fifth interlayer insulating film is reduced. The shape of the connecting hole is shaped so that its opening has a larger diameter at its upper position. The surfaces of the fifth interlayer insulating film and metallic plug are exposed to plasma atmosphere containing oxygen, irradiated with the light having a wavelength of several 10 nm to 400 nm or subjected to the sputter etching using an Ar gas.Type: GrantFiled: January 11, 2001Date of Patent: September 10, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshifumi Takata, Shigeru Harada, Hiroki Takewaka
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Publication number: 20020093097Abstract: There is provided a W plug formation method which prevents occurrence of a clearance or void around a W plug after HF cleansing as well as occurrence of an increase in resistance of a via hole and that of a contact hole, and occurrence of open failures. A surface layer section of a Ti film-which has been formed as barrier metal film in a hole formed in an interlayer dielectric film on a lower interconnection-is oxidized by means of oxygen plasma processing, thereby forming a Ti oxide film. Thus, the surface of the Ti film is not exposed on the surface. There can be prevented elution of the Ti film, which would otherwise be caused by HF cleansing effected in a subsequent process, and occurrence of a clearance or void, which would otherwise arise around a conductive plug.Type: ApplicationFiled: July 24, 2001Publication date: July 18, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takao Kamoshima, Takashi Yamashita, Yoshifumi Takata
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Publication number: 20020074587Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.Type: ApplicationFiled: April 19, 2001Publication date: June 20, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
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Publication number: 20010052650Abstract: A fourth and a fifth interlayer insulating film are formed and a connecting hole which passes through these films is formed. The connecting hole is filled with a metallic plug. The exposed surface of the fifth interlayer insulating film and metallic plug is etched back by dry etching in an atmosphere containing CF4 gas. Thus, the step difference between the surfaces of the metallic plug and fifth interlayer insulating film is reduced. The shape of the connecting hole is shaped so that its opening has a larger diameter at its upper position. The surfaces of the fifth interlayer insulating film and metallic plug are exposed to plasma atmosphere containing oxygen, irradiated with the light having a wavelength of several 10 nm to 400 nm or subjected to the sputter etching using an Ar gas.Type: ApplicationFiled: January 11, 2001Publication date: December 20, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yoshifumi Takata, Shigeru Harada, Hiroki Takewaka
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Publication number: 20010050440Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.Type: ApplicationFiled: July 13, 2001Publication date: December 13, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
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Patent number: 6319812Abstract: Sintering is effected a gate insulating film of a transistor in a hydrogen atmosphere at a temperature from 450° C. to 600° C. only before formation of an interconnection layer such as an aluminum interconnection layer which is less resistant to heat treatment at a temperature of 450° C. or more. Thereby, a method of manufacturing a semiconductor device can bring about sufficient recovery of a gate insulating film from process damages and others while preventing an adverse effect on the interconnection layer less resistant to the heat treatment at a high temperature.Type: GrantFiled: May 24, 2000Date of Patent: November 20, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Anma, Yoshinori Tanaka, Yoshifumi Takata
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Patent number: 6278187Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.Type: GrantFiled: July 27, 1998Date of Patent: August 21, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
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Publication number: 20010008311Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.Type: ApplicationFiled: January 10, 2001Publication date: July 19, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
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Patent number: 5712140Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.Type: GrantFiled: March 25, 1997Date of Patent: January 27, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Ishii, Yoshifumi Takata, Akihiko Ohsaki, Kazuyoshi Maekawa