Patents by Inventor Yoshiharu Hirata
Yoshiharu Hirata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927860Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: GrantFiled: April 11, 2022Date of Patent: March 12, 2024Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Patent number: 11804498Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.Type: GrantFiled: May 21, 2020Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
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Publication number: 20230317739Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.Type: ApplicationFiled: April 4, 2023Publication date: October 5, 2023Inventors: Hajime IMAI, Tohru DAITOH, Yoshihito HARA, Tetsuo KIKUCHI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20230307465Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: ApplicationFiled: May 18, 2023Publication date: September 28, 2023Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
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Patent number: 11695020Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: GrantFiled: December 11, 2020Date of Patent: July 4, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
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Patent number: 11668987Abstract: A display device includes a switching element having a pixel connection portion, a first insulating film having a first pixel contact hole formed therein so as to be in a place overlapping at least a part of the pixel connection portion, a common line, an intermediate electrode composed of the same conducting film as the common line, disposed to overlap the first pixel contact hole, and connected to the pixel connection portion, a common electrode not connected to the intermediate electrode but connected to the common line, a second insulating film having a second pixel contact hole formed therein so as to be in a place overlapping at least a part of the intermediate electrode, and a pixel electrode disposed so that at least a part of the pixel electrode overlaps the second pixel contact hole.Type: GrantFiled: April 28, 2021Date of Patent: June 6, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tohru Daitoh
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Publication number: 20230082232Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.Type: ApplicationFiled: September 6, 2022Publication date: March 16, 2023Inventors: Tatsuya KAWASAKI, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Yoshiharu HIRATA, Yoshihito HARA
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Patent number: 11569324Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.Type: GrantFiled: June 4, 2021Date of Patent: January 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Publication number: 20220342246Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: ApplicationFiled: April 11, 2022Publication date: October 27, 2022Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Patent number: 11476282Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.Type: GrantFiled: August 4, 2020Date of Patent: October 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
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Publication number: 20220283674Abstract: An in-cell touch panel includes a plurality of source lines, a source redundant line, a touch sensor line formed in the same layer as the plurality of source lines or the source redundant line, an organic insulating layer formed in a layer above the touch sensor line, and a common electrode formed in a layer above the organic insulating layer. A contact hole in which part of the common electrode is arranged is formed in the organic insulating layer above the touch sensor line, and the common electrode is connected to the touch sensor line via the contact hole.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: MASAKI MAEDA, TOHRU DAITOH, HAJIME IMAI, YOSHIHITO HARA, TERUYUKI UEDA, YOSHIHARU HIRATA, TATSUYA KAWASAKI
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Publication number: 20220285405Abstract: An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.Type: ApplicationFiled: March 4, 2022Publication date: September 8, 2022Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Patent number: 11378035Abstract: An engine control device includes a processor configured to execute a fuel injection control including: a first fuel injection processing for injecting an amount of fuel according to a first intake air amount based on an intake air flow rate detected by an air flow sensor; and a second fuel injection processing for injecting an amount of fuel according to a second intake air amount based on a throttle opening degree detected by a throttle position sensor. The processor selects the first fuel injection processing when a pulsation rate of the intake air flow rate is equal to or lower than a pulsation rate threshold value, and selects the second fuel injection processing when the pulsation rate is higher than the pulsation rate threshold value. The pulsation rate threshold value is smaller when a temperature correlation value is low than when the temperature correlation value is high.Type: GrantFiled: October 1, 2020Date of Patent: July 5, 2022Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yoshiharu Hirata, Shintaro Hotta, Takashi Amano
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Patent number: 11215891Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.Type: GrantFiled: May 21, 2020Date of Patent: January 4, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Tatsuya Kawasaki, Teruyuki Ueda, Hajime Imai, Tohru Daitoh
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Publication number: 20210384276Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.Type: ApplicationFiled: June 4, 2021Publication date: December 9, 2021Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20210349340Abstract: A display device includes a switching element having a pixel connection portion, a first insulating film having a first pixel contact hole formed therein so as to be in a place overlapping at least a part of the pixel connection portion, a common line, an intermediate electrode composed of the same conducting film as the common line, disposed to overlap the first pixel contact hole, and connected to the pixel connection portion, a common electrode not connected to the intermediate electrode but connected to the common line, a second insulating film having a second pixel contact hole formed therein so as to be in a place overlapping at least a part of the intermediate electrode, and a pixel electrode disposed so that at least a part of the pixel electrode overlaps the second pixel contact hole.Type: ApplicationFiled: April 28, 2021Publication date: November 11, 2021Applicant: SHARP KABUSHIKI KAISHAInventors: YOSHIHITO HARA, HAJIME IMAI, MASAKI MAEDA, TATSUYA KAWASAKI, YOSHIHARU HIRATA, TOHRU DAITOH
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Patent number: 11079636Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.Type: GrantFiled: October 21, 2020Date of Patent: August 3, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshiharu Hirata, Yoshihito Hara, Hideki Kitagawa, Tatsuya Kawasaki, Masaki Maeda, Teruyuki Ueda, Yoshimasa Chikama, Hajime Imai, Tohru Daitoh
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Patent number: 11079643Abstract: An active matrix substrate includes: a source metal layer including a plurality of source bus lines; a lower insulating layer covering the source metal layer; a oxide semiconductor TFT including an oxide semiconductor layer provided on the lower insulating layer; an inter-layer insulating layer covering the oxide semiconductor TFT; a pixel electrode provided on the inter-layer insulating layer; a common electrode including a plurality of sub common electrodes each of which is capable of functioning as a touch sensor electrode; a gate metal layer including a plurality of gate bus lines and a gate electrode; a drain metal layer including the drain electrode; and a plurality of touch sensor lines included in the drain metal layer and each electrically connected to any one of the sub common electrodes.Type: GrantFiled: June 3, 2020Date of Patent: August 3, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Maeda, Tohru Daitoh, Hajime Imai, Yoshihito Hara, Hideki Kitagawa, Tatsuya Kawasaki, Teruyuki Ueda, Yoshiharu Hirata
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Publication number: 20210183899Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: ApplicationFiled: December 11, 2020Publication date: June 17, 2021Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
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Patent number: 11009758Abstract: A display panel displaying an image includes a first substrate, a second substrate disposed opposite the first substrate, electric optical substance sealed between the first substrate and the second substrate, a transistor disposed on the first substrate and supplying an electric signal to the electric optical substance and including an oxide semiconductor film as an activating layer, and a light blocking film disposed on the second substrate and blocking visible light from transmitting therethrough, the light blocking film having a hole in a position overlapping the transistor in a plan view.Type: GrantFiled: June 4, 2019Date of Patent: May 18, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshimasa Chikama, Jun Nishimura, Yoshiharu Hirata