Patents by Inventor Yoshiharu Kataoka

Yoshiharu Kataoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090174843
    Abstract: In a liquid crystal display device including a display liquid crystal panel and a viewing-angle-control liquid crystal panel and capable of switching viewing angle characteristics, a half wavelength plate for setting a viewing restricted direction is provided between the display liquid crystal panel and the viewing-angle-control liquid crystal panel. This makes it possible to realize a liquid crystal display device that allows a viewing restricted direction to be set as appropriate.
    Type: Application
    Filed: April 16, 2007
    Publication date: July 9, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takehiko Sakai, Tsuyoshi Okazaki, Katsuhiko Morishita, Yoshiharu Kataoka, Chikanori Tsukamura, Dai Chiba
  • Publication number: 20090102989
    Abstract: A display system includes a liquid crystal display (10) including a backlight (3), a liquid crystal display panel (1), and a viewing angle control panel (2) for controlling the viewing angle of the display panel (1), the display system causing the amount of external light reflected by the liquid crystal display (10) to be relatively larger than the amount of light leaked from the backlight (3) onto the liquid crystal display panel (1). This provides a display system having an enhanced blocking effect.
    Type: Application
    Filed: December 21, 2006
    Publication date: April 23, 2009
    Inventors: Takehiko Sakai, Tsuyoshi Okazaki, Katsuhiko Morishita, Yoshiharu Kataoka, Chikanori Tsukamura, Takahiro Sasaki, Dai Chiba
  • Publication number: 20090102824
    Abstract: In an odd-shaped display whose display area is not rectangular in shape, a defect such as a reduction in the display quality due to the bright line or the like caused by the pixels that are located in a specific portion can be prevented. In an active matrix substrate used as a substrate of such an odd-shaped display in which the distribution area of the pixel electrodes corresponding to the display area has a shape other than rectangular, at least one dummy gate line is formed outside the gate line that is located at the outermost edge on the scanning start side. For peripheral pixels connected to the gate line and the gate line that lies on the scanning end side of the gate line, the gate lines located one row above the respective gate lines are extended on the opposite side of each of the peripheral pixels from the gate line to which the TFT of each of the peripheral pixels is connected. It is preferable that dummy pixels are located on the upper side of the individual peripheral pixels.
    Type: Application
    Filed: March 13, 2007
    Publication date: April 23, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shinya Tanaka, Yoshiharu Kataoka, Hajime Imai, Masaya Okamoto, Chikanori Tsukamura
  • Publication number: 20090096759
    Abstract: A touch panel includes an insulating substrate, a transparent touch electrode provided on the insulating substrate, and a frame portion connected to a periphery of the touch electrode. The touch panel detects a touched position on the touch electrode based on an electric signal through the frame portion. The frame portion is provided between the insulating substrate and the touch electrode.
    Type: Application
    Filed: January 31, 2007
    Publication date: April 16, 2009
    Inventors: Shogo Nishiwaki, Yoshiharu Kataoka, Toru Daito, Shinya Tanaka, Yukihiko Nishiyama, Shingo Kawashima, Hiroyuki Kaigawa, Takayuki Urabe
  • Publication number: 20090096954
    Abstract: A liquid crystal display includes a backlight (3), a liquid crystal display panel (1), and a viewing angle control panel (2) for controlling the viewing angle of the display panel (1), the liquid crystal display further including a lens sheet (41) provided between the backlight (3) and the liquid crystal display panel (1). This provides a display device system which is capable of providing better blocking.
    Type: Application
    Filed: December 21, 2006
    Publication date: April 16, 2009
    Inventors: Takehiko Sakai, Tsuyoshi Okazaki, Katsuhiko Morishita, Yoshiharu Kataoka, Chikanori Tsukamura, Dai Chiba
  • Publication number: 20090046077
    Abstract: A display device includes: a first substrate and a second substrate disposed to face each other; a display medium layer interposed between the first substrate and the second substrate; a plurality of pixel electrodes arranged in a matrix between the first substrate and the display medium layer; a first transparent electrode, interposed between the second substrate and the display medium layer, for detecting a touched location; and a second transparent electrode, interposed between the first transparent electrode and the display medium layer, for receiving a display signal. The display device detects the touched location using a capacitive coupling method and displays an image. A shield electrode for suppressing capacitive coupling is formed between the first transparent electrode and the second transparent electrode.
    Type: Application
    Filed: September 28, 2006
    Publication date: February 19, 2009
    Inventors: Shinya Tanaka, Yoshiharu Kataoka
  • Patent number: 7476936
    Abstract: The substrate (10) of the present invention includes: a first electrode (26) and a second electrode (30). The second electrode (30) is formed on an insulation film (52) covering at least a part of the first electrode (26) and electrically connected with the first electrode (26) through a contact hole (50) formed in the insulation film (52). The first electrode (26) includes a laminated structure of a metal film (42) and a protective film (44). An etching rate of the metal film (42) is almost equal to an etching rate of the protective film (44) with respect to a first etching for forming the metal film (42) and the protective film (44). An etching rate of the protective film (44) is almost zero with respect to a second etching for forming the contact hole (50).
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: January 13, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masafumi Kokura, Yoshiharu Kataoka
  • Patent number: 7098046
    Abstract: A method for aligning existing layers formed prior to a new layer and the new layer in forming the new layer on a wafer 4, wherein a microscope 6 as a first measurement condition and a microscope 7 as a second measurement condition are used, and marks 4a and 4b formed in each of said existing layers are measured by switching the first and second conditions, and said existing layers and said new-layer are aligned based on measurement of mark position of each of said existing layers, and the microscope 7 has a plurality of measurement conditions as optical characteristics, and the measurement conditions are switched.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: August 29, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiharu Kataoka
  • Patent number: 7029727
    Abstract: A thin film transistor (TFT) is formed on an insulating substrate, and a photosensitive resin film as an interlayer insulating film is formed so as to cover the TFT. Contact holes are formed in the photosensitive resin, and smooth concave and convex portions are provided on an upper surface of the resin. A film including molybdenum nitride (MoN) and a reflective pixel electrode film are successively laminated on the photosensitive resin. The nitrogen content in the MoN film may be between 5 atomic % and 30 atomic % inclusive.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 18, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masafumi Kokura, Yoshiharu Kataoka, Takayuki Shimada
  • Publication number: 20050255622
    Abstract: The substrate (10) of the present invention includes: a first electrode (26) and a second electrode (30). The second electrode (30) is formed on an insulation film (52) covering at least a part of the first electrode (26) and electrically connected with the first electrode (26) through a contact hole (50) formed in the insulation film (52). The first electrode (26) includes a laminated structure of a metal film (42) and a protective film (44). An etching rate of the metal film (42) is almost equal to an etching rate of the protective film (44) with respect to a first etching for forming the metal film (42) and the protective film (44). An etching rate of the protective film (44) is almost zero with respect to a second etching for forming the contact hole (50).
    Type: Application
    Filed: April 14, 2003
    Publication date: November 17, 2005
    Inventors: Masafumi Kokura, Yoshiharu Kataoka
  • Publication number: 20050190322
    Abstract: The etching composition of the invention is capable of simultaneously etching the films of a three-layered laminate film comprising an uppermost amorphous transparent electrode film made of IZO, etc., an intermediate reflective electrode film made of Al, etc. and a lowermost galvanic corrosion-inhibiting film made of Mo, etc. or a two-layered laminate film comprising an upper amorphous transparent electrode film and a lower reflective electrode film by a sole use thereof in a single etching operation to provide an etched laminate film having an edge of a good normal-tapered or stepwise shape. The etching composition comprises an aqueous water containing 30 to 40% by weight of phosphoric acid, 15 to 35% by weight of nitric acid, an organic acid and a cation-generating component.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 1, 2005
    Inventors: Satoshi Okabe, Taketo Maruyama, Masafumi Kokura, Yoshiharu Kataoka
  • Patent number: 6876435
    Abstract: In an exposure system, a predetermined wafer (5) is exposed with the first exposure layout by using a projection optical system (4) for projecting the pattern of a reticle (2) onto the wafer, an illumination device (10) and light-receiving device (11) for detecting a plurality of plane positions on the wafer (5), and a driving unit for driving the wafer (5) along the optical axis of the projection optical system (4). Prior to the second exposure with the second exposure layout at the second exposure field size, a position where a plane position is to be detected is determined on the basis of at least one of the first exposure field size, the first exposure layout, and underlayer information of the first exposure. Then, the plane position is detected.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: April 5, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshiharu Kataoka, Tai Hoshi
  • Patent number: 6838686
    Abstract: A method for aligning existing layers formed prior to a new layer and the new layer in forming the new layer on a wafer 4, wherein a microscope 6 as a first measurement condition and a microscope 7 as a second measurement condition are used, and marks 4a and 4b formed in each of said existing layers are measured by switching the first and second conditions, and said existing layers and said new layer are aligned based on measurement of mark position of each of said existing layers, and the microscope 7 has a plurality of measurement conditions as optical characteristics, and the measurement conditions are switched.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: January 4, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiharu Kataoka
  • Patent number: 6836140
    Abstract: A TEG (Test Element Group) block 1 includes a TFT (Thin Film Transistor) test element and a capacitance test element that are arranged adjacent to each other, and six test terminals. A TEG block 2 includes a resistance test element and a capacitance test element that are arranged adjacent to each other, and six test terminals. In these TEG blocks, the test terminals are arranged with the same pattern. Each of the test elements in each TEG block is connected to at least one of a plurality of test terminals included in that TEG block. The test elements can be efficiently formed on the substrate in view of the space on a display device substrate or the preference of characteristics to be evaluated. Moreover, characteristics of each test element can be conducted with a common probe regardless of the type of display device.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: December 28, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Fujikawa, Yoshiharu Kataoka, Hitoshi Matsumoto
  • Publication number: 20040174510
    Abstract: A method for aligning existing layers formed prior to a new layer and the new layer in forming the new layer on a wafer 4, wherein a microscope 6 as a first measurement condition and a microscope 7 as a second measurement condition are used, and marks 4a and 4b formed in each of said existing layers are measured by switching the first and second conditions, and said existing layers and said new layer are aligned based on measurement of mark position of each of said existing layers, and the microscope 7 has a plurality of measurement conditions as optical characteristics, and the measurement conditions are switched.
    Type: Application
    Filed: March 17, 2004
    Publication date: September 9, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshiharu Kataoka
  • Patent number: 6568978
    Abstract: A method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of performing a plasma treatment of the organic insulating region; forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 27, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiharu Kataoka, Takashi Fujikawa, Masafumi Kokura
  • Publication number: 20020166982
    Abstract: A predetermined wafer (5) is exposed with the first exposure layout by using a projection optical system (4) for projecting the pattern of a reticle (2) onto the wafer, an illumination device (10) and light-receiving device (11) for detecting a plurality of plane positions on the wafer (5), and a driving unit for driving the wafer (5) along the optical axis of the projection optical system (4). Prior to the second exposure with the second exposure layout at the second exposure field size, a position where a plane position is to be detected is determined on the basis of at least one of the first exposure field size, the first exposure layout, and underlayer information of the first exposure. Then, the plane position is detected.
    Type: Application
    Filed: April 23, 2002
    Publication date: November 14, 2002
    Applicant: Canon Kabushiki Kaisha
    Inventors: Yoshiharu Kataoka, Tai Hoshi
  • Patent number: 6473156
    Abstract: A scanning exposure apparatus includes a first movable stage movable while carrying a first object thereon, a second movable stage movable while carrying a second object thereon, a projection optical system, a scanning system for scanningly moving the first and second stages relative to the projection optical system to project a pattern of the first object onto the second object, reference plates provided on the first movable stage and having predetermined patterns, a detecting system for detecting positions of the reference plates with respect to an exposure optical axis direction of the projection optical system, a measuring system for measuring a position of the first movable stage with respect to a scan direction, a storing system for storing therein the positions with respect to the optical axis direction as detected by the detecting system and the position with respect to the scan direction at the corresponding moment, and a correcting system for correcting, during the scan of the first and second objec
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: October 29, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiharu Kataoka
  • Publication number: 20020079920
    Abstract: A TEG (Test Element Group) block 1 includes a TFT (Thin Film Transistor) test element and a capacitance test element that are arranged adjacent to each other, and six test terminals. A TEG block 2 includes a resistance test element and a capacitance test element that are arranged adjacent to each other, and six test terminals. In these TEG blocks, the test terminals are arranged with the same pattern. Each of the test elements in each TEG block is connected to at least one of a plurality of test terminals included in that TEG block.
    Type: Application
    Filed: October 26, 2001
    Publication date: June 27, 2002
    Inventors: Takashi Fujikawa, Yoshiharu Kataoka, Hitoshi Matsumoto
  • Publication number: 20020034831
    Abstract: A method for aligning existing layers formed prior to a new layer and the new layer in forming the new layer on a wafer 4, wherein a microscope 6 as a first measurement condition and a microscope 7 as a second measurement condition are used, and marks 4a and 4b formed in each of said existing layers are measured by switching the first and second conditions, and said existing layers and said new layer are aligned based on measurement of mark position of each of said existing layers, and the microscope 7 has a plurality of measurement conditions as optical characteristics, and the measurement conditions are switched.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 21, 2002
    Inventor: Yoshiharu Kataoka